Network-on-Chip (NoC) has been proposed as an attractive alternative to traditional dedicated busses in order to achieve modularity and high performance in the future System-on-Chip (SoC) designs. Recently, endto-end congestion control has gained popularity in the design process of network-on-chip based SoCs. This paper addresses a congestion control scenario under traffic mixture which is comp...

Networks-on-Chip (NoC) design is a trade-off between cost and performance. To realize the best trade-off between these factors, researchers have recently proposed using network partitioning techniques to customize the NoC architecture according to the application requirements. In this paper, the impact of using partitioning on different NoC metrics; namely, power, area, and delay, is analyzed. ...

A Scalable hierarchical architecture based Code-Division Multiple Access (CDMA) is proposed for high performance Network-on-Chip (NoC). This hierarchical architecture provides the integration of a large number of IPs in a single on-chip system. The network encoding and decoding schemes for CDMA transmission are provided. The proposed CDMA NoC architecture is compared to the conventional archite...

Nowadays, with technology shrinking and the huge demand for supporting multiple applications has led designers to use multiple IP cores within a single chip. Therefore, the designers have proposed Networks-on-chip to overcome the problems of future complex systems. Mapping IPs directly affects NoC design parameters such as latency and power consumption. In this paper we present a power and perf...

Network-on-chip (NoC) performance largely depends on the underlying deadlock-free and efficient routing algorithm. The effectiveness of any adaptive routing algorithm strongly depends on the underlying selection strategy. When the routing function returns a set of admissible output channels with cardinality greater than one, a selection function is used to select the output channel to which the...

The use of fault-tolerant mechanism is essential to ensure the correct functionality of integrated circuits after manufacturing due to the massive number of faults that may occur during the process. In this work, we propose a set of fault-tolerant techniques to cope with faulty wires in Network-on-Chip (NoC). The most appropriate technique is chosen by taking into account the number of faulty w...

This paper presents a performance model for predicting average message latency under uniformly distributed traffic in a hypercube based network-on-chip (NoC). Unlike previous works, the model obtains service rate for incoming traffic at a particular channel of a node by calculating reverse service rate provided by downstream nodes, and has simple closed-form calculation to produce accurate anal...

The Network-on-Chip (NoC) approach is a promising solution to the increasing complexity of on-chip communication problems due to its high scalability. A NoC architecture design with ultra-low latency and high throughput is critical in order to support a wide range of applications. In this paper, we propose novel spatial-based NoC resource allocation algorithms to reduce the communication conges...

Improving Efficiency of Embedded Multi-core Platforms with Scratchpad Memories Johny Paul, Walter Stechele, Manfred Kröhnert, and Tamim Asfour 12:00 – 12:30 Position Paper & Discussion: Towards Actor-oriented Programming on PGAS-based Multicore Architectures Sascha Roloff, Frank Hannig, and Jürgen Teich 12:30 – 13:30 Lunch Break 13:30 – 14:30 Multi-Objective Diagnosis of Non-Permanent Faults in...

Chip multiprocessors (CMPs) with on-chip network connecting processor cores have been pervasively accepted as a promising technology to efficiently utilize the ever increasing density of transistors on a chip. Communications in CMPs require invalidating cached copies of a shared data block. The coherence traffic incurs more and more significant overhead as the number of cores in a CMP increases...