The ultimate focus of this paper is to provide a hyperchaos-based reconfigurable platform for the real-time securing communicating embedded systems interconnected in networks according Internet Things (IoT) standards. proposed platform’s Register Transfer Level (RTL) architecture entirely developed and designed from scratch using VHSIC Hardware Description Language (VHDL). original idea consist...

In this paper, we propose a method to synthesize hardware from highlevel programming language description. The main step of the proposed method is to localize global variables. The localization of global variables is essential in synthesizing hardware from high-level programming language description because global variables cannot be synthesized directly. We first preprocess the input descripti...

In this work, a simplified startup method for AC synchronous machines is solved by means of a simplified algorithm based only in feeding the AC synchronous machine with stator voltages with a ramp frequency. The implementation of the algorithm along with the Space Vector Pulse Width Modulation technique is carried out by means of a Field Programmable Gate Array (FPGA) device, where Very High Sp...

This paper proposes a field-programmable gate array (FPGA)-based integrated circuit (IC) for computing apparent powers and power factors of power systems. In a nonsinusoidal and unbalanced three-phase power system, the calculation of apparent powers and power factors has many definitions. Load characteristics of harmonic and unbalance can not be expressed in the traditional apparent power and p...

A new configuration realizing water quality monitoring device using ISFET involving low power CMOS Integrated “Ion Sensitive Field Effect transistor (ISFET)—Operational Amplifier is presented. The study’s main focus is on simulation of power and performance analysis of ISFET device, which is used for water quality monitoring. This approach can improve calibration of device to a fairly wide rang...

We propose an efficient hardware architecture design & implementation of Advanced Encryption Standard (AES). The AES algorithm defined by the National Institute of Standard and Technology (NIST) of United States has been widely accepted. The cryptographic algorithms can be implemented with software or built with pure hardware. However Field Programmable Gate Arrays (FPGA) implementation offers ...

Convolution is fundamental operation of most of the signal processing systems. It is necessity of time to speed up convolution process at very appreciable extent. Here Direct method of computing the discrete linear convolution of finite length sequences is used. The approach is easy to learn because of the similarities to computing the multiplication of two numbers by a pencil and paper calcula...

This paper presents a high-level hardware design environment called Pollux. A design description is written with the Lustre data-ow language, and used by the diierent Pollux tools to produce the corresponding synchronous circuit or, for example, a simulation program, that can be compiled and executed on a sequential machine. Lustre has been chosen because it is well-suited to hardware descripti...