Digital hardware is treated as a collection of interacting parallel components. The ANISEED method (Analysis In SDL Enhancing Electronic Design) uses SDL (Specification and Description Language) to specify and analyse timing characteristics of hardware designs. A library contains specifications of typical components in single/multi-bit and untimed/timed forms. Timing may be specified at an abst...

We investigate the relationship between timed c/e systems 4] and timed automata 2]. We provide an eeective function that associates to each timed c/e system an \equivalent" timed automaton. Equivalence has to be understood here as describing essentially the same real{time behaviors. A beneet from providing such a function is that analysis tools developed for timed automata can now be applied to...

Timed systems, such as timed automata, are usually analyzed using their operational semantics on timed words. The classical region abstraction for timed automata reduces them to (untimed) finite state automata with the same time-abstract properties, such as state reachability. We propose a new technique to analyze such timed systems using finite tree automata instead of finite word automata. Th...

We de ne robust timed automata, which are timed automata that accept all trajectories \robustly": if a robust timed automaton accepts a trajectory, then it must accept neighboring trajectories also; and if a robust timed automaton rejects a trajectory, then it must reject neighboring trajectories also. We show that the emptiness problem for robust timed automata is still decidable, by modifying...