The implementation of analog CMOS circuits that operate in the very low power supply voltage range (1 V to 2 V) becomes more important nowadays. Most accurate filter circuits are designed in the switched-capacitor technique. The existing design techniques require, however, the on-chip generation of a higher voltage by means of a voltage multiplier. In this paper, a novel technique, derived from...

In this paper, a 0.18-V input three-stage charge pump circuit applying forward body bias is proposed for energy harvesting applications. In the developed charge pump, all the MOSFETs are forward body biased by using the inter-stage/output voltages. By applying the proposed charge pump as the startup in the boost converter, the kick-up input voltage of the boost converter is reduced to 0.18 V. T...

The realization of line and load regulation in switchedcapacitor (SC)-based converters is discussed. A duty-cycle control is based on partial charging of the capacitors in the circuit. The influence on the efficiency is pointed out. The use of inductors in SC-based converters is discussed.

The Switched Capacitor (SC) Integrator mentioned in this paper, is part of a test chip that has been designed in 0.5 μm CMOS technology. With this novel test structure, precision investigations on major nonidealities in such a circuit can be performed. Keywords— SC integrator, analog CMOS switch, channel charge, clock feed-through.

Presented in this paper is a low power, area efficient reconfigurable analog-to-digital (ADC) converter, utilising a charge-summation technique with a switched-capacitor implementation. Using a non-inverting switched-capacitor integrator a staircase ramp is produced using switching capacitors and a fixed reference voltage, as opposed to a linear ramp. The advantage of the charge summation techn...

An analog versatile neuroimage processor (VNIP) architecture is proposed here. VNIP can process various types of neural network and image processing structures, without any hardware modification. The structure allows unlimited expansion of network size and the compensation of process variation. The proof-of-concept chip is implemented, using a combination of continuous-time multiplier and switc...

A double-sampling highpass delta-sigma modulator (HPDSM) with inherent frequency translation is presented. The switched-capacitor highpass filter with double-sampling not only minimizes the number of capacitors required in the feedback network but also enables chopper stabilization which makes the modulator immune to 1/f noise and DC offset. A first-order prototype HPDSM with 3bit quantization ...