Cache performance is critical to the overall performance of modern CPUs. In most processors, cycle time is almost entirely determined by the cache hit time. This places practical limits on the complexity of cache controllers. Because of the growing gap between CPU performance and memory access times, the cost of a cache miss in CPU cycles is growing steadily [1]. As a result, it becomes critica...

hyperion hyperspectral data contains a very rich source of information from the earth surface that collects 242 narrow contiguous spectral bands. achieving this source of rich information is subject to the performance of suitable image processing methods on raw satellite data. satellite image processing methods can be classified into two categories of statistical-based and spectral-based. in th...

despite the extensive deployment of multi-core architectures in the past few years, the design and optimization of each single processing core is still a fresh field in computing .on the other hand, having a design procedure (used to solve the problems related to the design of a single processing core )makes it possible to apply the proposed solutions to specific-purpose processing cores .the i...

High performance processors make use of caches to increase the rate at which they can process the data. Soft errors can corrupt the information in the memory especially in cache memory which is the closest data storage to the CPU. Cache tag field are critical to correctness of cache access and to achieve high hit rate. Complex protection mechanism to tag bit information can degrade the performa...

This paper evaluates the Triplet Based Architecture, TriBA – a new idea in chip multiprocessor architectures and a class of Direct Interconnection Network (DIN). TriBA consists of a 2D grid of small, programmable processing units, each physically connected to its three neighbors so that advantageous features of group locality can be fully and efficiently utilized. Any communication model can be...

EEcient instruction and data caches are extremely important for achieving good performance from modern high performance processors. Conventional cache architectures exploit locality, but do so rather blindly. By forcing all references through a single structure, the cache's eeectiveness on many references is reduced. This paper presents a selective caching scheme for improving cache performance...

The amount of power dissipated by the implementation of an algorithm, for instance in the form of a dedicated chip-set, is considered to be one of the most important constraints for the selection of a high performance graphics algorithm. This is due to the fact that the realization of computational capability within the reach of one Tera operations per second is non-practical with general purpo...

Over the past several decades, much research has been done in the area of modeling, simulating, and measuring the performance of locking primitives under conditions of low and high contention and with attention to memory locality of the locking data structures. Most of the existing locking primitives are not fair with respect to lock grants and can cause lock starvation among CPUs during high c...

This paper investigates a variant of the work-stealing algorithm that we call the localized work-stealing algorithm. The intuition behind this variant is that because of locality, processors can benefit from working on their own work. Consequently, when a processor is free, it makes a steal attempt to get back its own work. We call this type of steal a steal-back. We show that the expected runn...

We propose an auxiliary strategy, called per-user caching, for locating users who move from place to place while using Personal Communications Services (PCS). The caching strategy augments the basic location strategy proposed in existing standards such as GSM and IS-41, with the objective of reducing network signaling and database loads in exchange for increased CPU processing and memory costs....