0038-1101/$ see front matter 2008 Elsevier Ltd. A doi:10.1016/j.sse.2008.06.045 * Corresponding author. Tel.: +32 10 47 8134; fax: E-mail addresses: [email protected] (D. Bo vain.be (R. Ambroise), [email protected] ( [email protected] (J.-D. Legat). For ultra-low-power applications, digital integrated circuits may operate at low frequency to reduce dynamic power consumption. At high ...

This paper proposes a method to reduce static power consumption in Adiabatic logic circuits based on Complementary Pass transistor Adiabatic Logic (CPAL) operated by two phase power clocks. We are applying power gating MTCMOS technique to reduce static power consumption in CPAL circuits. We tested MTCMOS power gating technique on 4-bit ripple carry adder to observe effect of static power reduct...

The management of power consumption for battery life is widely considered to be the limiting factor in supporting the concurrent operation of high performance, complex applications on mobile platforms. At 65nm and below, minimizing the static power dissipation through aggressive techniques such as coarse grain MTCMOS power gating and threshold voltage scaling can yield these significant reducti...

The Triple gate FinFET architecture has emerged as a viable contender for the ultimate scalability of CMOS devices. FinFET structure offers better control over device leakage currents than the conventional bulk MOSFET structure. In this paper, we present the 6 transistor (6T) SRAM cell implementation using the 22 nm gate length FinFET devices modeled using a 3-D device simulator. The performanc...

Estimation and Synthesis for Low Power, High Performance Integrated Circuits by Premal Buch Doctor of Philosophy in Engineering Electrical Engineering & Computer Sciences University of California, Berkeley Professor A. Richard Newton, Chair Power minimization is becoming very important for a number of reasons ranging from an increasing demand for portable computing to the problem of hot chips d...

A self-timed radix-2 division scheme for low power consumption is proposed. By replacing dual-rail dynamic circuits in non-critical data paths with single-rail static circuits, power dissipation is decreased, yet performance is maintained by speculative remainder computation. SPICE simulation results show that the proposed design can achieve 33.8-ns latency for 56-bit mantissa division and 47% ...

A high-speed low-power flash analog-to-digital converter is designed and optimized in a 0.13μm CMOS technology. The ADC consumes 65mW with a supply voltage of 1.2V at 1.2G samples per second. Static DNL and INL are 0.1 LSB and 0.2LSB respectively. The figure of merit shows 1.3pJ per conversion step. The simulation result of the full flash ADC shows improvement in nonlinearity and power dissipat...

Design flexibility and power consumption in addition to the cost, have always been the most important issues in design of integrated circuits. Power dissipation and energy consumption are especially important when there is a limited amount of power budget or limited source of energy. Recently advances in VLSI Technology have made it possible to put a complete System on Chip (SOC) which facilita...

| A CMOS interface circuit to transfer a digital signal between two circuits of di erent supply voltages is described. The interface can be used, for example, between 3 volt and 5 volt or higher voltage families. The principal characteristics of the interface circuit are: no static power dissipation, high speed, and high speed bu ering [1].

A novel low power and low transistor count static energy recovery full adder (SERF) is presented in this paper. The power consumption and general characteristics of the SERF adder are then compared against three low power full adders; the transmission function adder (TFA), the dual value logic (DVL) adder and the fourteen transistor (14T) full adder. The proposed SERF adder design was proven to...