This study presents the design of low power 9T SRAM cell using dynamic domino logic to achieve low power dissipation. The internal structure of the proposed 9T SRAM has cross coupled dynamic inverters which periodically updates the internal node voltage levels which, increase the read and write stability of the circuit. The SRAM design also has charge keeper transistor which resolves the proble...

Based on the observation that dynamic occurrence of zeros in the cache access stream and cacheresident memory values of ordinary programs exhibit a strong bias towards zero, this paper presents a novel CMOS five-transistor SRAM cell (5T SRAM cell) for very high density and low power cache applications. This cell retains its data with leakage current and positive feedback without refresh cycle. ...

The self-improvement of static random access memory (SRAM) cell stability by post-fabrication high-voltage stress is experimentally demonstrated and its mechanism is analyzed using 4k device-matrixarray (DMA) SRAM test element group (TEG). It is shown that the stability of unbalance cells is automatically improved by merely applying stress voltage to the VDD terminal of SRAM. It is newly found ...

The primary motivation behind aggressive device scaling is to achieve improved performance and increased integration. These improvements come at the cost of increased sensitivity to PVT variations and standby leakage, particularly in area-constrained circuit such as SRAM that employs minimum-geometry devices. An attempt is made in this work to mitigate these problems in traditional 6T SRAM cell...

The main issue in VLSI design are optimizing speed, scaling in silicon technology and increased packing density. These issues account for increased power dissipation in SoC (System on Chips) making them unsuitable for portable operations. Since SRAM consist of almost 60% of VLSI circuits, hence, it is needed that a low power SRAM design to maximize the run time with minimum requirements on size...

This paper introduces a novel half-select resilient dual write wordline 8T (DW8T) SRAM with a sequential writing technique. The dual write wordlines are sequentially activated in a write cycle, and its combination with the half-VDD precharge suppresses the half-select problem. We implemented a 256-Kb DW8T SRAM and a half-VDD generator with a 40-nm CMOS process. The measurement results of the se...

The comparison and analysis of SRAM cells provides vital information for trading of design parameters to meet stringent requirements in the deep sub micron ranges. Initially this paper introduces to SRAM cells, then cell parametric dependences are investigated and finally simulation results of the same are shown. An 11T SRAM cell is compared with the conventional 6T SRAM cell for SNM, Power, DR...

This brief describes a new method to implement the singleport SRAM-based transpose memory for large size discrete cosine transform (DCT)/indiscrete cosine transform (IDCT) which are used in the latest video coding standard, such as high efficiency video coding. Instead of shift-register array or multiport SRAM, only single-port SRAM is used in the proposed design. A new diagonal data mapping sc...

In this paper a detailed study of the effect of the phase of noise has been done on 6T SRAM cell. The 6T SRAM has been subjected to different combinations of noises at the storage nodes and the read ability and write ability of the SRAM cell is examined considering different noise voltage levels. It is found that the effect is different under different combinations of the phases of the noise vo...

The explosive growth of battery operated devices has made lowpower design a priority in recent years Moreover, embedded SRAM units have become an important block in modern SoCs. Present day SRAMs are striving to increase bit counts while maintaining low power consumption and high performance. To achieve these objectives there is a need of continuous scaling of CMOS transistors, and so the proce...