The functional units SPICE-models design steps of the controller K1156EU2 using Micro-Cap 12 computer assisted circuit software. Presented methodology includes analysis units. Developed models are used as baseline components for controllers’ SPICE-macromodel. and respective key characteristics aligned with represent fully all claimed hardware counterparts’ specifications. Each model can be tune...

A new compact but accurate Verilog-A model for MultiLevel-Cell Phase-change RAMs is proposed in this paper. The previous circuit-based SPICE macromodel has to have a very complicated circuit to describe multi-level resistance thus it needs a long simulation time and occupies large computer memories. This new Verilog-A model can easily model the multi-level resistance by using the partial SET an...

The COVID-19 pandemic shows an irreversible change in the world. Developing nations like India, effect is even more significant. Spice exports are one of important sectors to generate foreign revenue country. This paper investigated impact on spice India. research based secondary data from fiscal year 2018-19 2020-21. To analyse conditional volatility a time series data, GARCH model was applied...

A unified, macroscopic, one-dimensional model is presented for the quantitative description of the process of dielectric charging in RF MEMS switches. The fidelity of the model relies upon the utilization of experimentally-obtained data to assign values to model parameters that capture the non-linear behavior of the dielectric charging process. The proposed model can be easily cast in the form ...

In this paper we have put forward an analytical model, which could accurately capture the on chip interconnect delay. As we move onto higher frequency range, of the order of GHz, the effects of shunt conductance cannot be ignored, as it provides a measure of the possible leakage. Due to this reason, we have derived our on-chip interconnect delay metric considering distributed RLCG segments, rat...

We develop an analytical delay model based on rst and second moments to incorporate inductance e ects into the delay estimate for interconnection lines. Delay estimates using our analytical model are within 15% of SPICE-computed delay across a wide range of interconnect parameter values. We also extend our delay model for estimation of source-sink delays in arbitrary interconnect trees. For the...

These electrical simulation programs have grown out of SPICE. SPICE is an acronym that stands for Simulation Program for IC Emulation. This is a tool originally intended to aid in the understanding of the performance of integrated circuits (ICs). Today, SPICE modeling has moved well beyond integrated circuit emulation to full circuit emulation with some packages also allowing for environmental ...

The paper “SPICE Model of Photomultiplier Tube Under Different Bias Conditions” is commented. We revisit the mathematical formulation to compensate for some ambiguities in original manuscript, and point out inconsistencies results reproducibility simulations, as well optimized parameters originally obtained with PSPICE simulation engine. All simulations are recalculated NGSPICE software using c...

Simulation of dynamic phosphor space charge in alternating-current thin-film electroluminescent (ACTFEL) devices is performed using SPICE equivalent circuit models. Two SPICE equivalent circuits are developed; one for the case of space charge creation via impact ionization and another for field emission. Both SPICE equivalent circuits are based on modeling the space charge distribution as a sin...