An analog queue-based architecture and an adaptive digital-calibration algorithm calibrate an 8-bit two-stage pipelined algorithmic analog-to-digital converter (ADC). To minimize power dissipation and noise, the queue consists of only one sample-and-hold amplifier. At a sampling rate of 20 Msamples/s, the peak signal-to-noise-and-distortion ratio (SNDR) is 45 dB, and the spurious-free dynamic r...

This work describes a 10-bit 40MS/s pipelined analog-to-digital converter (ADC) which is used in IEEE 802.11a WLAN system. This pipelined ADC is consisted of one sample-and-hold (S/H) circuit and nine uniform pipelined stages. In this pipelined ADC, the resolution for the S/H circuit and each single pipelined stage is up to 12 bit and 14 bit respectively at 8 MHz input frequency. The spurious f...

The recent rapid development of digital wireless systems has led to the need for multistandard, multichannel radio-frequency (RF) transceivers. This paper presents the relationship between the performance of a bandpass-sampling analog-to-digital converter (ADC) and the requirements of a digital intermediate-frequency receiver for a wide-band code-division multiple-access (WCDMA) base station. A...

Coordinate rotation digital computer (CORDIC) is an efficient algorithm for computations of trigonometric functions. Scaling-free-CORDIC is one of the famous CORDIC implementations with advantages of speed and area. In this paper, a novel direct digital frequency synthesizer (DDFS) based on scaling-free CORDIC is presented. The proposed multiplier-less architecture with small ROM and pipeline d...

This paper proposes a very simple method of eliminating the gain and offset errors caused by mismatches of elements, such as capacitors, for a high-speed CMOS pipelined ADC with a 1.5-bit architecture. The gain and offset errors in a bit-block due to capacitor mismatch are analog-to-digital (A-D) converted without correcting errors, but by exchanging capacitors at every clock. The obtained resu...

An input-dependent integral nonlinearity (INL) model is developed for pipeline ADC post-correction. The INL model consists of a static and dynamic part. The INL model is subtracted from the ADC digital output for compensation. Static compensation is performed by adjacent sets of gains and offsets. Each set compensates a certain output code range. The frequency content of the INL dynamic compone...

This paper presents the design of low power modulator and demodulator circuits dedicated to a BFSK transceiver, operating in the 863870 MHZ ISM band. The two circuits were designed using ams 0.35μm technology with 3V dc voltage supply. Simulation results of the new Direct Digital Frequency Synthesizer in the modulation have shown good performances of the designed system as the Spurious Free Dyn...

Abstract In this paper, a 12-bit 100MS/s digital-to-analog converter (DAC) is presented, where segmented current steering technique employed. A “4+8” architecture used compromising the advantages and disadvantages of binary-weighted thermometer-coded DACs. Cascode source cascode switch to achieve high input impedance minimize output glitches for good linearity dynamic performance. The simulatio...

A 10 bit 1 MS/s SAR ADC with one LSB common-mode shift energy-efficient switching scheme for image sensor is presented. Based on the two sub-capacitor arrays architecture and technique, proposed achieves 98.45% less energy over conventional in LSB. The comparator uses a low power dynamic comparator. sampling switch adopts bootstrap circuit error. logic composed of Bit-Slice consumption few tran...