Random pattern testing methods are known to result in poor fault coverage for most sequential circuits unless costly circuit modiications are made. In this paper we propose a novel approach to improve the random pattern testability of sequential circuits. We introduce the concept of holding signals at primary inputs and scan ip-ops of a partially scanned sequential circuit for a certain length ...

x y z x y xy♁z Abstract – To construct a reversible sequential circuit, reversible sequential elements are required. This work presents novel designs of reversible sequential elements such as D latch, JK latch, and T latch. Based on these reversible latches, we construct the designs of the corresponding flip-flops .Comparing with previous work, the implementation cost of our new designs, includ...

Self-checking circuits can detect the presence of both transient and permanent faults. A self-checking circuit consists of a functional circuit, which produces encoded output vectors, and a checker, which checks the output vectors. The checker has the ability to expose its own faults as well. The functional circuit can be either combinational or sequential. A self-checking system consists of an...

The paper presents functional delay test generation approach for non-scan synchronous sequential circuits. The non-scan sequential circuit is represented as the iterative logic array model consisting of k copies of the combinational logic of the circuit. The value k defines the number of clock cycles. The software prototype model is used for the representation of the function of the circuit. Th...

In this paper, we propose a modeling technique that captures the dependence of the power dissipation of a (combinational or sequential) logic circuit on its input/output signal switching statistics. The resulting power macromodel consists of a quadratic or cubic equation in four variables, that can be used to estimate the power consumed in the circuit for any given input/output signal statistic...

Power consumption of any circuit is high during test mode than its normal mode of functioning. Different techniques are proposed to reduce the test power. This paper presents the consolidated research work carried to reduce the test power. Usually the power dissipation is due to the sequential and combinational elements presents in the circuit. In this paper we proposed different methodologies ...