In this paper, a development of sensor node for environment monitoring is described. The Reconfigurable System-On-chip (RSOC) technology is used to integrate the node’s main components on FieldProgrammable Gate Array (FPGA) chip. The main components required to support the environmental applications such as pixels sensor, reconfigurable processing core, and a tiny solar unit for recharging node...

This paper describes a complete FPGA implemented intrinsic evolvable system which is employed as a novel approach to automatic design of spatial image filters for two given types of noise. The genotype-phenotype representation of the proposed evolvable system is inspired by the Cartesian Genetic Programming and the function level evolution. The innovative feature of the proposed system is that ...

To promote the commercial implementation of software download for Software Defined Radio (SDR) terminals, a secure method of download is vital. Downloading of all the relevant software is performed via a public channel, and accordingly the security issue of the downloading is one of the key issues. For the purpose of security, it is necessary to ensure privacy, integrity, and authentication. Th...

A run-time reconfigurable multiply-accumulate (MAC) architecture is introduced. It can be easily reconfigured to trade bitwidth for array size (thus maximizing the utilization of available hardware); process signed-magnitude, unsigned or 2’s complement data; make use of part of its structure or adapt its structure based on the specified throughput requirements and the anticipated computational ...

With the increasing use of information technology for different societal goals, the demand for flexible and multiple-functionality appliances has risen. Making technology reconfigurable could be a way of achieving this. This working paper is written against the background of a large scale research project developing reconfigurable sensors in order to achieve a continuous and affordable infrastr...

In the last years reconfigurable computing grew from a niche application to an important R&D scene. But also today most architectures lack essential features for the convenient use as a co-processing unit. E.g. embedded accelerator design with traditional FPGAs is very similar to sophisticated ASIC-design due to the bit-level granularity of FPGAs. In this paper important topics for reconfigurab...

The X4CP32 is an architecture that combines both Parallel and reconfigurable paradigms. It consists of grid of Reconfigurable and Programming Unit (RPU), responsible for all the processing and program flow. This paper presents architectural modification in order to maximize the computational use of the Cells in a RPU. A change to a very large instruction word (VLIW) philosophy in the RPU was im...

Now a days space vehicles and other electronic hardware also demands that the architectures should be small, speed in operation, low power consumption, small in area and be reconfigurable in unexpected environments. The evolvable hardware (EHW) or evolutionary algorithm used to design the desired circuit automatically. Genetic algorithm is the commonly used evolutionary algorithm. EHW, because ...

In this paper, we present the analysis of applications from the domain of handheld and wearable computing. This analysis is the first step to derive and evaluate design parameters for dynamically reconfigurable processors. We discuss the selection of representative benchmarks for handhelds and wearables and group the applications into multimedia, communications, and cryptography programs. We si...

This paper proposes a novel RF front-end architecture for software-defined radios (SDRs) based on an electronically tunable antenna pair controlled by an antenna control unit (ACU) consisting of field effect transistor (FET) switches and a field programmable gate array (FPGA). The fundamental gain-bandwidth limitations of electrically small antennas prevent a small antenna from having high effi...