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This paper presents a reconfigurable cable parallel robot, which spatial topology can be reconfigured through managing the branch numbers and the hoisting points of the end-effector. An experimental prototype of the reconfigurable cable parallel robot is designed and developed. A typical configuration of the reconfigurable cable parallel robot is analyzed as a case study. The finite element ana...

Reconfigurable Manufacturing Systems (RMSs) offer a key technology for the realization of mass customization. Compared with integral systems, RMS may provide system configurations to satisfy a wide range of Functional Requirements (FRs). An important issue for RMS is configuration design, the determination of a configuration from all of feasible configurations to meet FRs. Configuration design ...

The computing resources available on dynamically partially reconfigurable devices increase every year enormously. In the near future, we expect that many applications run on a single reconfigurable device. In this paper, we present a concept for multitasking on dynamically partially reconfigurable systems called virtual area management. We explain its advantages, show its challenges, and discus...

Reconfigurable computing maps computation onto flexible and reprogrammable hardware. A typical reconfigurable computing (RC) system consists of a host processor (with a traditional architecture) and one or more reconfigurable coprocessors. Proposed hardware architectures for reconfigurable co-processors fall in two broad categories [4]: netlist computers with uniform arrays of fine grained logi...

This paper presents the architectural design of a reconfigurable and extensible Very Long Instruction Word (VLIW) processor. In addition to architectural extensibility, our processor also supports reconfigurable operations. Furthermore, we present an application development framework to optimally exploit the freedom of reconfigurable operations. Because our processor is based on the VEX ISA, we...

ASIPs and reconfigurable processors are architectural choices to extend the capabilities of a given processor. ASIPs suffer from fixed hardware after design, while ASIPs and reconfigurable processors suffer from the lack of a pre-established instruction set, making them difficult to program. As intermediate choice, reconfigurable coprocessors systems (RCSs) contain dedicated hardware (coprocess...

This paper studies the difference in computational power between the mesh-connected parallel computers equipped with dynamically reconfigurable bus systems and those with static ones. The mesh with separable buses (MSB) is the meshconnected parallel computer with dynamically reconfigurable row/column buses. The broadcast buses of the MSB can be dynamically sectioned into smaller bus segments by...

This paper introduces a design technique for coarse-grained reconfigurable architectures targeting digital signal processing (DSP) applications. The design procedure is analyzed in detail and an areatime-power efficient reconfigurable kernel architecture is presented. The proposed technique inlines flexibility into custom carry-save (CS) arithmetic datapaths exploiting a stable and canonical in...