The Electron Counting (EC) paradigm was proved to be an efficient methodology for computing arithmetic operations in Single Electron Tunneling (SET) technology. In previous research EC based addition and multiplication have been implemented. However, the effective performance of these schemes is diminished by fabrication technology imposed practical limitations. To alleviate this problem high r...

Advances in nanoelectronic fabrication have enabled integrated circuits to operate at a high frequency. The finite impulse response (FIR) filter needs only to meet real-time demand. Accordingly, increasing the FIR architecture’s folding number can compensate the high-frequency operation and reduce the hardware complexity, while continuing to allow applications to operate in real time. In this w...

Abstract This paper describes a static 16x16-bit 2’s complement wireless baseband multiplier testchip in 1.2V, 90nm dual-Vt CMOS technology. One-hot Booth encoding, sum/delay difference optimized 3:2 compressor tree, and signal-profile optimized final adder schemes are employed to achieve 1GHz, 22mW operation at 1.2V, scalable to 500MHz, 3mW at 0.8V. Introduction Short bit-width (≤16-bit) radix...

This paper explains the design and implementation of 8-bit ALU (arithmetic and logic unit) using VHDL by using mixed style of modeling in Xilinx ISE 8.1i. The ALU takes two8-bits numbers and performs different principal arithmetic and logic operations like addition, multiplication, logical AND, OR, XOR, XNOR, NOR. The major focus of concern in this ALU is the multiplication operation using radi...

Two’s complement multipliers are performance and power-critical components for wireless baseband signal processing applications. Parallel clusters of multiplier, multiply-add, multiply-accumulate cores are required to perform complex filter operations in Fast Fourier Transform (FFT) accelerators while consuming ultra low energy/operation [1]. A 12x9b single-cycle two’s complement twiddle multip...

due to its simplicity radix-2 is a popular algorithm to implement fast fourier transform. radix - 2 p algorithms have the same order of computational complexity as higher radices algorithms, but still retain the simplicity of radix-2 . by defining a new concept, twiddle factor template , in this paper we propose a method for exact calculation of multiplicative complexity for radix-2 p algorithm...

Most of the signal processing algorithms using floating point arithmetic, which requires millions of operations per second to be performed. For such stringent requirement design of fast, precise and efficient circuit is needed. This article present an IEEE 754 floating point unit using carry look ahead adder and radix-4 modified Booth encoder multiplier algorithm and the design is compared in t...

The main objective of the proposed work is implementing the 32 bit Vedic and Baugh-Wooley multiplication operation with Carry-Save methodology to reduce the average time and delay of operations. This system contain a high speed low power digital multiplier by using advantage of Vedic multiplication algorithms with a very efficient leakage control technique called multiple channel conventional m...

Finite Impulse Response (FIR) digital filters have potential for high-speed and low-power realization through parallel processing on FPGA. In this paper, an efficient implementation of FIR filters, which uses a Booth Radix-8 multiplier, is suggested. For implementation of the said FIR filter MATLAB FDATool is employed to determine various filter coefficients. The 8 order FIR filters have been d...