This paper reports on the design solutions and the different measurements we have done in order to characterize the thermal coupling and the performance of differential temperature sensors embedded in an integrated circuit implemented in a 65 nm CMOS technology. The on-chip temperature increases have been generated using diode-connected MOS transistors behaving as heat sources. Temperature meas...

To protect integrated circuits against IP piracy, Physically Unclonable Functions (PUFs) are deployed. PUFs provide a specific signature for each integrated circuit. However, environmental variations, (e.g., temperature change), power supply noise and more influential IC aging affect the functionally of PUFs. Thereby, it is important to evaluate aging effects as early as possible, preferentiall...

FPGA companies are amongst the earliest adopters of next-generation integrated circuit process technology, as the economics of scaling are more favorable for FPGAs than for many other technologies. Moving to advanced processes involves many challenges, including power management, device modeling, increasing I/O performance to match the computational capacity, and enabling very large designs to ...

Only a few devices are not yet compatible with SMT principles: a few "exotic" components like large capacitors, resistors, inductors, varistors, etc. and almost all the power semiconductor packages. Several drawbacks are associated with existing power packages: by P. Casati & C. Cognetti A New High Power IC Surface Mount Package Family: PowerSO-20TM & PowerSO-36 Power IC Packaging from Insertio...

Amount of power consumption is one of the important measures of performance of an integrated circuit. CMOS is the latest technology which is in use till date. This paper gives an overview of the power dissipation occurring in CMOS circuit. The paper then describes the advantages and limitations of power optimization techniques of CMOS. As we go deeper into the nanometer scale, MOS transistors f...

This paper presents the design and simulation of a 5GHz monolithic low-noise amplifier integrated with an active Balun. Intended to WLAN applications, the fully integrated circuit was implemented in a 0.18μm CMOS technology. The simulations, optimized to noise performance, gain and minimum differential phase and magnitude error, were performed with BSIM3 model. Circuit simulations present 23dB ...

With the advancement of CMOS technology, the trend is to design transceivers using this technology with the aim of achieving full integration and reduced system cost. The power amplifier (PA) being one of the most important blocks of the wireless communication system is no exception. The aim of this work is to provide the study that allow the design of a singleended RF CMOS Class-E power amplif...

Phase-locked-loop in radiofrequency and mixed signal integrated circuit experience noise as electromagnetic interference coupled on input and power supply which translates to the timing jitter. Most of PLL noise analysis did not take into account the ageing effect. However device ageing can degrade the physical parameters of transistors and makes noise impact worse. This paper deals with the an...

In this paper, a current-mode square/triangular wave is presented. Due to operation in current-mode, the proposed circuit provides a wide frequency response, a low supply voltage, low power consumption and electronic controllability. Thus, it is very suitable for use in portable and battery-powered equipments. The proposed square/triangular wave generator consists of merely current mode Schmitt...