For the problem arising in the design of integrated chips, an efficient heuristic approach was proposed. It unites the stages of placing the logical elements (devices) on the chip and performing their detailed routing. At that, it minimizes both the critical (maximum) delay and the chip area required for routing.

There is a high demand of space-efficient algorithms in builtin or embedded softwares. In this paper, we consider the problem of designing space-efficient algorithms for computing the maximum area empty rectangle (MER) among a set of points inside a rectangular region R in 2D. We first propose an inplace algorithm for computing the priority search tree with a set of n points in R using O(logn) ...

We present evidence of the efficiency in an emergent futures market before, during and following the Asian crisis. Our approach is to comprehensively test price formation and informational efficiency in markets which play a leading role in the price discovery process. Our contribution is to examine the impact of the Asian crisis from a derivative markets perspective, thereby furthering the deba...

A stochastic model for interconnections in integrated circuits composed of unequal size logic blocks separated by routing channels is described. An algorithm, based on the model, is given for estimating channel widths and chip area. The effectiveness of the algorithm is tested through an example. Applications of the model to placement and routing of integrated circuits are discussed.

ion Layers logic transistor layout physical L L L L e.g. Hamming weight assumption e.g. single gates simulation e.g. post place and route simulations e.g. actual measurements implementation protocol algorithm Circuit abstraction levels ⇔ useful for a simulation based approach Limit due to : Going deeper in the abstraction levels ⇒ different amount of information due to more realistic scenarios....

In this paper, we present a fast and eficient compilation methodology for pipeline reconfigurable architectures. Our compiler back-end is much faster than conventional CAD tools, and fairly eficient. W e represent pipeline reconfigurable architectures by a generalized VLI W-like model. The complex architectural constraints are effectively expressed in terms of a single graph parameter: the rout...

The present research investigated the mechanisms guiding habitual behavior, specifically, the stimulus cues that trigger habit performance. When usual contexts for performance change, habits cannot be cued by recurring stimuli, and performance should be disrupted. Thus, the exercising, newspaper reading, and TV watching habits of students transferring to a new university were found to survive t...