Database systems frequently have to execute a batch of related queries. Multi-query optimization exploits evaluation plans that share common results. Current approaches to multi-query optimization assume there is infinite disk space, and very limited memory space. Pipelining was the only option considered for avoiding expensive disk writes. The availability of fairly large and inexpensive main ...

Software pipelining is a classic compiler optimization that improves the performances of inner loops on instruction-level parallel processors. In the context of embedded computing, applications are compiled prior to manufacturing the system, so it is possible to invest large amounts of time for compiler optimizations. Traditionally, software pipelining is performed by heuristics such as iterati...

With the escalation of clock frequencies and the increasing ratio of wire to gate delays clock skew is a major problem to be overcome in tomorrow s high speed VLSI chips Also with an increasing number of stages switching simultaneously comes the problem of higher peak power consumption In our past work we have proposed a novel scheme called Counter ow Clocked C Pipelining to combat these proble...

Out-of-program-order execution has become almost a ubiquitous characteristic of modern processors because of its ability to tolerate variable memory-instruction latency. As designs are becoming increasingly power-conscious, the cost and complexity of the components of out-of-order execution are becoming problematic. Compilers have generally proven adept at planning useful static instruction-lev...

Software pipelining is an attractive method to schedule code for processors that exhibit instruction-level parallelism such as pipelined, super-scalar, and (V)LIW machines. It has been implemented for a variety of processors ( e.g. FPS-164[10], Warp[9], Cydra-5[7]), and a number of pipelining algorithms have been described in the literature. Software pipelining produces a schedule so that the e...

Many parallel algorithms exhibit a hypercube communication topology. Such algorithms can easily be executed on a multicomputer with a hypercube interconnection topology. However, in most cases these parallel algorithms only make use of a small fraction of the interconnection bandwidth offered by the multicomputer. In particular, each processor of a hypercube multicomputer is connected to d diff...

In this paper, a new high speed control circuit is proposed which will act as a critical path for the data which will go from input to output to improve the performance of wave pipelining circuits The wave pipelining is a method of high performance circuit designs which implements pipelining in logic without the use of intermediate registers. Wave pipelining has been widely used in the past few...