This paper presents a novel 1.8 V digital-to-analog converter (DAC) which is designed to operate at DC for a wide variety of circuit calibration techniques. To achieve 10-bit performance at 1.8 V, an ultra high gain op-amp is introduced for servoing. In order to minimize area consumption while maximizing performance, a segmented plus binary plus R-2R architecture is used. The DAC was designed i...

The accuracy of integrated sensors is often limited by errors of the electronic interface; this is the case in most low voltage–low power integrated sensor systems. In this paper we describe the dynamic op amp matching (DOAM) technique; the circuits using the dynamic op amp matching (DOAMCs) are a new type of circuits using dynamic element matching (DEMCs). In comparison with traditional DEMCs ...

A technique for low-voltage CMOS analog circuit design is presented in this paper. In this technique, voltage sources are added in series with the gates of the MOS transistors to lower the effective threshold voltages of the transistors. With the lowered effective threshold voltage, it is possible to build a host of analog circuit that operates with a decreased supply voltage. A 0.6V ultra-low ...

A high-swing, high-performance CMOS telescopic operational amplifier is described. The high swing of the op-amp is achieved by employing the tail and current source transistors in the deep linear region. The resulting degradation in differential gain, common-mode rejection ratio (CMRR), and other amplifier characteristics are compensated by applying regulatedcascode differential gain enhancemen...

Transimpedance amplifiers using voltage feedback operational amplifiers are widely used for current to voltage conversion in applications when a moderatehigh bandwidth and a high sensitivity are required, such as photodiodes, photomultipliers, electron multipliers and capacitive sensors. The conventional circuit presents a virtual earth to the input and at low frequencies, the input capacitance...

This paper addresses the issues involved in designing 1V Op-amp in standard digital CMOS technology. Bulk-driving technique is used to circumvent the metal–oxide semiconductor field-effect transistor turn-on (threshold) voltage requirement. The Op-amp will be designed in a Europractice 0.7μm n-well CMOS process having threshold voltage of 0.76V and –1V for NMOS and PMOS respectively. Simple and...

We are developing low power cryogenic readout integrated circuits (ROICs) for large format far-infrared image sensors using fully-depleted-silicon-on-insulator (FD-SOI) CMOS technology. We have evaluated the characteristics of MOS FETs fabricated by the FD-SOI CMOS technology and have found that both p-ch and n-ch FETs show good static performance below the liquid helium temperature, where n-ch...

An 8th-order continuous-time (CT) bandpass delta-sigma (AZ) modulator has been designed and simulated in a 65 nm CMOS process. This modulator achieves in simulation 25 MHz signal bandwidth at 250 MHz center frequency with a signalto-noise ratio (SNR) of 75.5 dB. The modulator samples at 1 GS/s while consuming 319 mW. On the system level, the feedback topology secures stability for the 8th-order...

The designing of charge pump with high gain OpAmp is a challenging task for getting faithful response .Design of high performance phase locked loop require ,a design of high performance charge pump .We have designed a operational amplifier for reducing the error caused by high speed glitch in a transistor and mismatch currents . A separate Op-Amp has designed in 180 nm CMOS technology by CADENC...