C-based cycle-accurate simulations are used to evaluate the performance of a Network-On-Chip (NoC) based on an improved version of the modified Fat Tree topology. The modification simplifies routing further and guarantee orderly reception of packets without any loss of performance. Several traffic models have been used in these simulations; Bursty and non-bursty traffic with uniformlydistribute...

The performance of network-on-chip (NOC) largely depends on the underlying routing techniques. A routing technique has two constituencies: output selection and input selection. This paper focuses on the improvement of input selection part. Two traditional input selections have been used in NOC, firstcome-first-served (FCFS) input selection and Round-Robin input selection. Also, recently a conte...

General purpose routing algorithms for a network-on-chip (NoC) platform may not be able to provide sufficient performance for some communication intensive applications. This may be because of low adaptivity offered by a general purpose routing algorithm resulting in some links getting highly congested. In this study the authors demonstrate that it is possible to design highly efficient applicat...

Three-Dimensional Networks-on-Chip (3D-NoC) has been presented as an auspicious solution merging the high parallelism of Network-on-Chip (NoC) interconnect paradigm with the high-performance and lower interconnect-power of 3-dimensional integration circuits. However, 3D-NoC systems are exposed to a variety of manufacturing and design factors making them vulnerable to different faults that cause...

Higher core counts and increasing focus on energy efficiency in modern Chip Multiprocessors (CMP) have led to renewed interest in simple and energy-efficient Network-on-Chip (NoC) designs. Several recent proposed designs trade off network capacity for efficiency, based on the observation that traditional networks are overprovisioned for many workloads. Bufferless routing is one such example. Ho...

By increasing, the complexity of chips and the need to integrating more components into a chip has made network –on- chip known as an important infrastructure for network communications on the system, and is a good alternative to traditional ways and using the bus. By increasing the density of chips, the possibility of failure in the chip network increases and providing correction and fault tol...

The latency, power consumption, and interconnect routing problems of NoCs can be simultaneously addressed by replacing multi-hop wired paths with high-bandwidth single-hop long-range wireless links. In this talk, we will present design of the millimeter (mm)-wave wireless NoC architectures. We will present detailed

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This paper is aimed to present a detailed description of the main factors which must be considered for task mapping onto Network on Chip (NoC) systems. A survey of the most representative and outstanding reported works is presented, along with conclusions and future work regarding such a review.