This paper outlines the design and analysis of a crossbar-type interconnection network that can be used with off-the-shelf microprocessor components to construct a four-processor/eight-memory module multiprocessor system. The only custom component is an interconnection (ICN) chip presently being fabricated by the authors. The ICN chip integrates 4 x 8 crosspoints for a 3-bit bus slice together ...

The Proteus architecture is a highly parallel MIMD, multiple instruction multiple data, machine, optimized for large granularity tasks such as machine vision and image processing. The system can achieve 20 G-flops (80 G-flops peak). It accepts data via multiple serial links at a rate of up to 640 megabytes/second. The system employs hierarchical reconfigurable interconnection network with the h...

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The Proteus architecture is a highly parallel MIMD, multiple instruction multiple data, machine, optimized for large granularity tasks such as machine vision and image processing. The system can achieve 20 G-flops (80 G-flops peak). It accepts data via multiple serial links at a rate of up to 640 megabytes/mnd. The system employs hierarchical reconfigurable interconnection network with the high...

Previous studies have shown that the interconnection network of a Chip-Multiprocessor (CMP) has significant impact on both overall performance and energy consumption. Moreover, wires used in such interconnect can be designed with varying latency, bandwidth and power characteristics. In this work, we present a proposal for performance-and energy-efficient message management in tiled CMPs by usin...

With the increasing use of Network of Workstations (NOWs) as an alternative to huge parallel computers it has become essential to design high-performance interconnection networks for the communication between the nodes of these clusters. A large number of studies have been carried out to achieve this objective. Most of them propose a new technique that affects one of the parameters that charact...

Parallel processing is an efficient form of information processing system,which emphasizes the exploitation of concurrent events in the computing process. To achieve parallel processing it’s required to develop more capable and cost-effective systems.In order to operate more efficiently a network is required to handle large amount of traffic. Multi-stage Interconnection Network plays a vital ro...

New advances in reconfigurable optical interconnect technologies will allow the fabrication of cheap, fast and run-time adaptable networks for connecting processors and memory modules in large shared-memory multiprocessor machines. Since the switching times of these components are typically high compared to the memory access time, reconfiguration can only take place on a time scale significantl...

Many problems today need the computing power that is only available by using large scale parallel processing. For a signi cant number of these problems, the density of the global communications between the individual processors, dominates the performance of the whole parallel implementation on a distributed memory multiprocessor system. In these cases, the design of the interconnection network ...

The report describes an environment for performing experiments in distributed processing. It replaces an earlier (1985) report, reflecting changes in the system and terminology. Our system offers researchers an easy way to design, implement, and test parallel algorithms. It provides software tools which make possible a variety of connection structures between processes. These process structures...