Adders and multipliers are two main units of the computer arithmetic processors and play an important role in reversible computations. The binary multiplier consists of two main parts, the partial products generation circuit (PPGC) and the reversible parallel adders (RPA). This paper introduces a novel reversible 4×4 multiplier circuit that is based on an advanced PPGC with Peres gates only. Ag...

A 4x4 bit multiplier is demonstrated based on the Chinese abacus. As comparing the simulation result of this work with the speed and power consumption of the 4x4 bits Braun array multiplier, the delays of the 4-bit abacus multiplier are 19.7% and 10.6% less than that of Braun array multiplier with 0.35μm and 0.18μm technologies, respectively. Meanwhile, the power consumption of the 4-bit abacus...

A 4x4 and 8x8 bit multiplier is demonstrated based on the Chinese abacus. As comparing the simulation result of this work with the speed of the 4x4 and 8x8 bits Braun array multiplier, the delays of the 8-bit abacus multiplier are 14% and 7.5% less than that of Braun array multiplier with 0.35μm and 0.18μm technologies, respectively. Meanwhile, the power consumption of the 8-bit abacus multipli...

Two’s complement multipliers are important for a wide range of applications. Paper describes a technique to reduce by one row the maximum height of the partial product array generated by Radix-4 Booth’s multiplier, without any increase in the delay of the partial product generation stage. The design of 8 bit and 16 bit multiplication scheme using different types of multiplier like Array multipl...

Multiplier is one of the essential element for all digital systems such as digital signal processors, microprocessors etc. In this paper, a new high speed multiplier using booth recoding technique is presented. This algorithm can be implemented by using the radix-8 booth recoding process. The proposed multiplier reduces the partial product array by almost 3/4 th the size of the bits. This reduc...

the present paper is an attempt to: 1- demonstrate how money is created (by the nature of the system), and to estimate the inflation resulting from monetary factors in both usurious and non-usurious systems. operational aspects of islamic and non-islamic banking systems are compared. 2- introduce a corrective term to be added to the multiplier of the supply of money, in order to prevent the und...

in this paper, we introduce the notion of multiplier in -algebra and study relationships between multipliers and some special mappings, likeness closure operators, homomorphisms and ( -derivations in -algebras. we introduce the concept of idempotent multipliers in bl-algebra and weak congruence and obtain an interconnection between idempotent multipliers and weak congruences. also, we introduce...

Physical limitations of Complementary Metal-Oxide-Semiconductors (CMOS) technology at nanoscale and high cost of lithography have provided the platform for creating Quantum-dot Cellular Automata (QCA)-based hardware. The QCA is a new technology that promises smaller, cheaper and faster electronic circuits, and has been regarded as an effective solution for scalability problems in CMOS technolog...

We present results for pseudodifferential operators on Rd whose symbol a(·,ξ) is almost periodic (a.p.) for each ξ ∈ Rd and belongs to a Hörmander class Sm ρ,δ. We study a linear transformation a 7→ U(a) from a symbol a(x,ξ) to a frequency-dependent matrix U(a)(ξ)λ,λ′ , indexed by (λ,λ′) ∈ Λ×Λ where Λ is a countable set in Rd . The map a 7→ U(a) transforms symbols of a.p. pseudodifferential ope...

The paper presents the concepts behind the "Urdhva Tiryagbhyam Sutra" and "Nikhilam Sutra" multiplication techniques. It then shows the architecture for a 16×16 Vedic multiplier module using Urdhva Tiryagbhyam Sutra. The paper then extends multiplication to 16×16 Vedic multiplier using "Nikhilam Sutra" technique. The 16×16 Vedic multiplier module using Urdhva Tiryagbhyam Sutra uses four 8×8 Ved...