This paper presents a design method for three-level programmable logic arrays (PLAs), which have input decoders and two-input EXOR gates at the outputs. The PLA realizes an EXOR of two sum-ofproducts expressions (EX-SOP) for multiple-valued input two-valued output functions. We developed an output phase optimization method for EXSOPs where some outputs of the function are minimized in the compl...

This paper shows the best operators for sumof-products expressions. We first describe conditions of functions for product and sum operations. We examine all two-variable functions and select those that meet the conditions and then evaluate the number of product terms needed in the minimum sum-of-products expressions when each combination of selected product and sum functions is used. As a resul...

To further increase the speed of computation, this paper aims to design and implement digital circuits entirely within the domain of multi-valued logic. In a fourvalued logic circuit, each wire carries two bits at a time, each logic gate operates two bits at once, and each memory cell records two bits at one time. To make the multi-valued computation possible, this paper describes a simple four...

there have been many productive methods developed so far for optimization of multiple response surface (mrs) problems. this paper tends to review the most seminal approaches in mrs and discuss the strength and weakness of each of the approaches through existing aspects in mrs. a numerical example is included to compare results by different methods. finally some of the prominent areas for future...

Complexity of silicon integrated circuits (IC) in very large scale of integration (VLSI) using binary logic is reaching a point where most of the silicon area is occupied with interconnecting lines among devices on the chip, which represents a drawback of the approach. First implication of the high wiring complexity is increased packing complexity with increased number of pins (in today's VLSI ...

We introduce a scheme to simplify a multi-valued network using redundancy removal techniques. Recent methods [1], [2] for binary redundancy removal avoid the use of state traversal. Additionally, [2] finds multiple compatible redundancies simultaneously. We extend these powerful advances in the field of binary redundancy removal to perform redundancy removal for multi-valued networks. First we ...

This paper considers methods to design multiple-output networks based on decision diagrams (DDs). TDM (time-division multiplexing) systems transmit several signals on a single line. These methods reduce: 1) hardware; 2) logic levels; and 3) pins. In the TDM realizations, we consider three types of DDs: shared binary decision digrams (SBDDs), shared multiple-valued decision diagrams (SMDDs), and...

Complex-valued signals are used in the modeling of many systems in engineering and science, hence being of fundamental interest. Often, random complex-valued signals are considered to be proper. A proper complex random variable or process is uncorrelated with its complex conjugate. This assumption is a good model of the underlying physics in many problems, and simplifies the computations. While...