With the enormous increase in portable cryptographic devices, physical attacks are becoming similarly popular. One of most common is Side-Channel Analysis (SCA), extremely dangerous due to its non-invasive nature. Threshold Implementations (TI) was proposed as first countermeasure provide provable security masked hardware implementations. While works on masking focused optimizing area requireme...

2. Latency. Latency, also known as delay, is a measure of the time it takes to traverse the network, including going through any intermediate routers. It represents the elapsed time between a sending node sending a packet and receiving node receiving that packet. For example, on my system, a local loopback (sending a packet back to the same machine) gives me a latency of 0.043 ms (milliseconds)...

This paper considers an optimisation problem encountered in the implementation of traffic policies on network routers, namely the ordering of rules in an access control list to minimise or reduce processing time and hence packet latency. The problem is formulated as an objective function with constraints and shown to be NP-complete by translation to a known problem. Exact and heuristic solution...

Significant challenges are posed in the design of routers and switches by explosive growth internet traffic stringent requirements for high availability research area computer networks. Ensuring both performance system is crucial. To achieve this, recent advancements have turned to utilization non-volatile memories, such as magnetic RAM (MRAM) phase-change memory (PCM), routing lookup tables pa...

High end routers are targeted at providing worst case throughput guarantees over latency. Caches on the other hand are meant to help latency not throughput in a traditional processor, and provide no additional throughput for a balanced network processor design. This is why most high end routers do not use caches for their data plane algorithms. In this paper we examine how to use a cache for a ...

Current router models [2, 3, 5, 6] assume that clock cycle time depends solely on router latency. However, in practice, routers are heavily pipelined, making cycle time largely independent of router latency. In this paper, we describe a router delay model that accurately accounts for pipelining based on technology-independent delay estimates derived through detailed gate-level analysis. Simulat...

In these days interaction between different network applications are becoming more popular and to improve the speed and datatransfer rate delay difference between the multynetworks should minimize. In this paper we propose a Latency EQualization (LEQ) service, which equalizes the perceived latency for all clients participating in an interactive network application. The few routers used in LEQ c...

The on-chip network (NoC) is a fundamental component of Non Uniform Cache Architectures and may significantly affect the performance of the overall system. The analysis described in this work evaluates the performance sensitivity of a single processor system adopting a NUCA L2 cache with respect to some NoC parameters, namely the hop latency and the buffering capacity of routers. The results sh...

This paper presents a novel loss recovery scheme, Active Reliable Multicast (ARM), for large-scale reliable multicast. ARM is “active” in that routers in the multicast tree play an active role in loss recovery. Additionally, ARM utilizes soft-state storage within the network to improve performance and scalability. In the upstream direction, routers suppress duplicate NACKs from multiple receive...