Image transmission using incoherent optical fiber bundles (IOFB) requires prior calibration to obtain the spatial in-out fiber correspondence in order to reconstruct the image captured by the pseudo-sensor. This information is recorded in a Look-Up Table (LUT), used later for reordering the fiber positions and reconstructing the original image. This paper presents a method based on line-scan to...

The main purpose of the method proposed in this article is to reduce number look-up-table (LUT) elements logic circuits sequential devices. devices are represented by models Mealy finite state machines (FSMs). Thesee so-called MPY FSMs based on two methods structural decomposition (the replacement inputs and encoding output collections). idea use types codes for implementing systems partial Boo...

A method is proposed which aims to reduce the hardware in FPGA-based circuits of Mealy finite state machines (FSMs). The a type structural decomposition method. Its main goal reducing number look-up table (LUT) elements FSM compared three-block circuit. idea using codes collections outputs for replacing inputs and variables. interstate transitions are defined generated two adjacent cycles synch...

This paper presents a novel discrete particle swarm optimization (PSO) for frequency response masking (FRM) finite impulse response (FIR) digital filters over the canonical signed-digit (CSD) multiplier coefficient space. A look-up table (LUT) scheme is employed to ensure that the PSO automatically searches through permissible CSD multiplier coefficient values in the course of optimization with...

Field Programmable Gate Array (FPGA) attributes of logic configurability, bitstream storage, and dynamic signal routing can be realized by leveraging the complementary benefits of emerging devices with Complementary Metal Oxide Semiconductor (CMOS)-based devices. In this paper, a novel Carbon/Magnet Lookup Table (CM-LUT) is developed and evaluated by trading off a range of mixed heterogeneous t...

This paper presents an efficient implementation of digit-serial/parallel multipliers on 4-input look-up table (LUT)-based field programmable gate arrays (FPGAs). This subset of FPGA devices hide individual gate delays and add important wiring delay. These two facts produce important changes over the theoretical advantages of each topology. Architectural transformations are applied to obtain top...

Due to wide power spectrums of rectangular data streams, it is important for base-band signals to be heavily band limited before modulation. That can be achieved by pulse shaping of rectangular bits. Some of the most common are a half-sine pulse shaper and a Gaussian pulse shaper which are used in Minimum Shift Keying (MSK), Gaussian Minimum Shift Keying (GMSK) and Gaussian Frequency Shift Keyi...

DCT-based digital video coding standards such as MPEG and H.26x have been widely adopted for multimedia applications. Thus video processing in the DCT domain usually proves to be more ef£cient than in the spatial domain. To directly convert an inter-coded frame into an intra-coded frame in the DCT domain, the problem of DCT domain inverse motion compensation was studied in [1]. Since the data i...

Among many existing algorithms, convergence methods are the most popular means of computing square root and the reciprocal of square root of numbers. An initial approximation is required in these methods. Look up tables (LUT) are employed to produce the initial approximation. In this paper a number of methods are suggested to reduce the size of the look up tables. The precision of the initial a...

The first implementation of a new programmable logic device using LUT(Look-Up Table) cascade architecture is developed in 0.35um CMOS logic process. Eight 64Kb asynchronous SRAMs are simply connected to form an LUT cascade with a few additional circuits. Benchmark results show that it has a competitive performance to FPGAs. 1. Introduction RAMs and PLAs (Programmable Logic Array) are used for p...