In this paper, is proposed a method to implement in FPGA (Field Programmable Gate Array) circuits different approximation of the sigmoid function. Three previously published piecewise linear and one piecewise second-order approximation are analyzed from point of view of hardware resources utilization, induced errors caused by the approximation function and bits representation, power consumption...

This paper presents experimental evidence for the need to create tighter links between logical and physical domains. Our experimental results show how gains reported by logic level optimizations|aimed at reducing the eeect of interconnect|fail to deliver after the circuits are placed and routed. We use functional exibilities represented by SPFDs 8] to remove redundant wires and nodes in circuit...

This is an experimental article which shows that logical correctness of logic circuits can be easily proven by the Mizar system. First, we define the notion of logic gates. Then we prove that an MSB carry of ’4 Bit Carry Skip Adder’ is equivalent to an MSB carry of a normal 4 bit adder. In the last theorem, we show that outputs of the ’4 Bit Carry Look Ahead Adder’ are equivalent to the corresp...

Delay computation in combinational logic circuits is complicated by the existence of unsensit-izable (false) paths and this problem is arising with increasing frequency in circuits produced by high-level synthesis procedures. Various sensitization conditions have been proposed in the past to eliminate false paths in logic circuits, but we use a recently developed single-vector condition, that i...

Logical Filtering is the problem of tracking the possible states of a world (belief state) after a sequence of actions and observations. It is fundamental to applications in partially observable dynamic domains. This paper presents the first exact logical filtering algorithm that is tractable for all deterministic domains. Our tractability result is interesting because it contrasts sharply with...

This paper explores different adder topologies for low power solutions. Furfher. we look at the energy optimization of circuits wing tramistor suing technique based on Logical Eflort. The efticienq of the method is verified on representative 16-bit adders, comnioitly found blocks in general purpose DSP processors. The results are shown and analyzed in the Energy-Delq space.

We propose a theoretical model to realize DNA made circuits based on in-vitro algorithms, to perform arithmetic and logical operations. The physical components of the resulting Arithmetic-Logic Unit are a variety of elements such as biochemical laboratories, test tubes and human operators. The advantage of the model is the possibility to perform arithmetic operations with huge binary numbers.