This paper describes an alternative approach to implement Computer Architecture Structures. It employs an array of identical devices that can be dynamically conngured by the application programmer. Known as \array of conngurable logic cells," this RAM-based FPGA ooers many research opportunities in the Computer Architecture area. The paper presents the design of an array of programmable devices...

This paper describes a novel Field Programmable Gate Array (FPGA) logic synthesis technique which determines if a logic function can be implemented in a given programmable circuit and describes how this problem can be formalized and solved using Quantified Boolean Satisfiability. This technique is general enough to be applied to any type of logic function and programmable circuit; thus, it has ...

In modern computing systems there is the need to utilize a large amount of data in maintaining high efficiency. Limited memory bandwidth, coupled with performance gap between and logic, impacts heavily on algorithms performance, increasing overall time energy required for computation. A possible approach overcome such limitations Logic-In-Memory (LIM). this paper, we propose LIM architecture ba...

Data types of Prolog are essentially restricted to terms at the cost of compactness and the unity of a logic programming language. On the other hand, it has been commonly recognized that Prolog has two practical problems, which considerably prevent the language and logic programming from being used for broader area of information processing. One problem is that Standard Prolog does not have the...

In this paper, a configurable single chip firing circuit for three phase motor speed control based on Field Programmable Gate Array (FPGA) hardware architecture is presented. The proposed circuit is designed, implemented and tested using MAX II PLD chip (EPM1270F256C5 device). The system has the advantages of being simple, flexible and low development cost with built-in self test. The experimen...

This report introduces a new systolic algorithm for the sequence alignment problem. This work builds upon an existing systolic array for computing the edit distance between two sequences. The alignment array is meant to be used as the second phase in a two-phase design with a modiied edit distance array serving as the rst phase. An implementation on the SPLASH programmable logic array is descri...