This paper describes a dual delay-locked loop architecture which achieves low jitter, unlimited (modulo 2 ) phase shift, and large operating range. The architecture employs a core loop to generate coarsely spaced clocks, which are then used by a peripheral loop to generate the main system clock through phase interpolation. The design of an experimental prototype in a 0.8m CMOS technology is des...

This paper presents analyses and experimental results on the jitter transfer of delay-locked loops (DLLs). Through a -domain model, we show that in a widely used DLL configuration, jitter peaking always exists and high-frequency jitter does not get attenuated as previous analyses suggest. This is true even in a firstorder DLL and an overdamped second-order DLL. The amount of jitter peaking is s...

This paper describes a low-voltage, low-jitter clock synthesizer and a temperaturecompensated tunable oscillator. Both of these circuits employ a self-correcting Delay-Locked Loop (DLL) which solves the problem of false locking associated with conventional DLLs. This DLL does not require the delay control voltage to be set on power-up, it can recover from missing reference clock pulses and beca...

Grid connected applications require an accurate estimate of the grid angle to feed power synchronously to the grid. This is achieved using a software phase locked loop (PLL). This application report discusses different challenges in the design of software phase locked loops and presents a methodology to design phase locked loops using C2000 controllers for single phase grid connection applicati...

This paper is a review of methods and techniques used for precise measurement of time intervals (TIs) or precise conversion of TIs to digital data. The following methods are described: the counter method and averaging, time stretching, time-to-amplitude conversion followed by analogue-to-digital conversion, the Vernier method, conversion utilizing tapped delay lines, and interpolation methods. ...

A half-rate reference-less clock and data recovery circuit is proposed, incorporating a coarse frequency-locked loop and a fine phase-locked loop with smooth switching to prevent adverse interaction and false locking. Fabricated in a 0.18-μm CMOS process, the recovered clock exhibits a peak-topeak jitter of 60ps for a 2-Gb/s PRBS-7 data and a phase noise of –93.5 dBc/Hz at 1-MHz offset. The cor...

Phase locked loop based feedback techniques are used in a variety of system level timing, control and communication applications. Re-configurable hardware and associated simulation models have been developed with an emphasis towards teaching the fundamentals of Phase locked loop systems. The material is hardware focussed and reinforces, control system theory, characterisation, design, and model...