In this paper, an artificial pollution test is carried out to study the leakage current of porcelain insulators. Fractal theory is adopted to extract the characteristics hidden in leakage current waveforms. Fractal dimensions of the leakage current for the security, forecast and danger zones are analyzed under four types of degrees of contamination. The mean value and the standard deviation of ...

In this paper, the effect of gate tunneling current in ultra-thin gate oxide MOS devices of effective length (Le ) of 25 nm ( oxide thickness = 1 1 nm), 50 nm ( oxide thickness = 1 5 nm) and 90 nm ( oxide thickness = 2 5 nm) is studied using device simulation. Overall leakage in a stack of transistors is modeled and the opportunities for leakage reduction in the standby mode of operation are ex...

The ever-growing leakage current of MOSFETs in nanometre technologies is the major concern to high performance and power efficient designs. Dynamic power management via powergating is effective to reduce leakage power, but it introduces power-up current that affects the circuit reliability. The authors present an in-depth study on high-level modelling of power-up current and leakage current in ...

A methodology is proposed to design low leakage registers by considering the type of timing path, i.e., short or long, and type of register, i.e., launching or capturing. Three different dual threshold voltage registers are developed where each register trades, depending upon the timing path, a different timing constraint for reducing the leakage current. For example, the first proposed registe...

To manage the increasing static leakage in low power applications, solutions for leakage reduction are sought at the device design and process technology levels. In this paper, 90nm, 70nm and 50 nm groovedgate nMOS devices are simulated using Silvaco device simulator. By changing the corner angle and adjusting few structural parameters, static leakage reduction is achieved in grooved nMOSFETS i...

Dramatic increase of subthreshold, gate and reverse biased junction band-to-band-tunneling (BTBT) leakage in scaled devices, result in the drastic increase of total leakage power in a logic circuit. In this paper a methodology for accurate estimation of the total leakage in a logic circuit based on the compact modeling of the different leakage current in scaled devices has been developed. Curre...

A high speed and low power CMOS inverter is designed & simulated in this paper. The critical path consists of PMOS and NMOS. The designed inverter cell offers high speed and low power consumption than the CMOS inverter. A Multi Threshold Complementary Metal Oxide Semiconductor (MTCMOS) technique is used to reduce the leakage current as well as leakage power to achieve better results. MTCMOS is ...

We propose a novel IDDQ outlier screening flow through a two-phase approach: a clustering-based filtering and an estimation-based current-threshold determination. In the proposed flow, a clustering technique first filters out chips that have high IDDQ current. Then, in the current-threshold determination phase, device-parameters of the unfiltered chips are estimated based on measured IDDQ curre...

This paper proposes a new heuristic approach to determine the input pattern that minimizes leakage currents of nanometer CMOS circuits during sleep mode considering stack and fanout effect. The proposed approach uses a new precise macro-modeling of leakage current considering subthreshold leakage, gate tunneling leakage, body effect, stack effect, and fanout effect. The macro-model is developed...

The power gating technique is useful in reducing standby leakage current, but it increases the gate delay. For a functional unit, its maximum allowable delay (for a target clock period) limits its smallest standby leakage current its power gating can achieve. In this paper, we point out that, in the high-level synthesis of a nonzero clock skew circuit, the resource binding (including functional...