This paper evaluates the Triplet Based Architecture, TriBA – a new idea in chip multiprocessor architectures and a class of Direct Interconnection Network (DIN). TriBA consists of a 2D grid of small, programmable processing units, each physically connected to its three neighbors so that advantageous features of group locality can be fully and efficiently utilized. Any communication model can be...

We examine the interaction between two interconnected networks (e.g., two local exchange carriers (LECs)) and a third network (e.g., an interexchange carrier (IXC)) seeking access to their customer base. The IXC could either interconnect with both LECs or interconnect with only one LEC and transit calls to the other LEC via the first LEC s network. We show that there is a wide set of cases in w...

A dynamic memory is a storage medium constituted by an array of cells and an interconnection network between them. It is characterized by the constant circulation of the stored data. The objective is to design the interconnection network in order to have small access times and a simple memory control. Several interconnection schemes have been proposed in the literature. This paper presents a qu...

Parallel processing is efficient form of information processing which means to implement high performance computing systems. A communication network that links processors and memory modules determines the efficiency of these parallel systems. To provide the required connectivity and performance at reasonable cost, an interconnection network is used. Hence, multistage interconnection networks ar...

This paper presents a hybrid shared memory architecture which combines the scalability of a multistage interconnection network with the contention reduction benefits of coherent caches. We achieve this by replacing the memory modules and final stages of a multistage interconnection network with clusters of coherent caches. The performance of Cache Coherent Hybrid Interconnected Memory Extension...

ÐIn their 1982 paper, Adams and Siegel proposed an Extra Stage Cube Interconnection Network that tolerates one switch failure with one extra stage. We extend their results and discover a class of Extra Stage Interconnection Networks that tolerate multiple switch failures with a minimal number of extra stages. Adopting the same fault model as Adams and Siegel, the faulty switches can be bypassed...

Computer systems capable of teraflop computation are becoming a near-term reality with the emergence of high-speed powerful processors that can run cooperatively in a multiprocessor system.. The underlying fabric that supports communication among processors in the system is the interconnection network. The basic function of an interconnection network is to transfer information from the input no...

    supply chain network   receding horizon control demand move suppression term   Supply chain networks are interconnection and dynamics of a demand network. Example subsystems, referred to as stages, include raw materials, distributors of the raw materials, manufacturers, distributors of the manufactured products, retailers, and customers. The main objectives of the control strategy for the s...

The Macro-star graph which has the star graph as a basic module has node symmetry, maximum fault tolerance, and hierarchical decomposition property. And, it is an interconnection network which improves a network cost against the star graph. A Matrix-star graph also has such a good properties of the Macro-star graph and is an interconnection network which has a lower network cost than the Macro-

The \Cross Product" technique introduced by Even and Litman EL92] is extended into a full decomposition theory enabling a unique (up to isomorphism) and polynomial factorization of layered interconnection networks (including most well-known networks) into a product of prime factors. A polynomial algorithm is provided for checking whether a given layered interconnection network is isomorphic to ...