This paper presents an efficient interconnect network for Mesh of Clusters (MoC) Field-Programmable Gate Array (FPGA) architecture. Compared to conventional MoC-based FPGA, proposed architecture improves the MoC-based interconnect in 2 ways. First, we optimize the intra-cluster interconnect topology by depopulating the intra-cluster full crossbar. Then, we propose a new multi-levels interconnec...

In a multi-user production cluster there is no control over the intra-cluster communication patterns, which can cause unanticipated hot spots to occur in the cluster interconnect. In a multistage interconnect a common side effect of such a hot-spot is the roll-over of the saturation to other areas in the interconnect that were otherwise not in the direct path of the primary congested element. T...

Field-Programmable Gate Arrays (FPGAs) are computational devices containing uncommitted logic and interconnect resources which users configure for the applications they wish to run. Because the potential applications for FPGAs are not known at the time that they are fabricated, manufacturers of FPGAs should ideally provide abundant amounts of both logic capacity and interconnect flexibility to ...

The microprocessor architecture transition from multi-core to many-core will drive increased chip-to-chip I/O bandwidth demands at processor/memory interfaces and in multi-processor systems. Future architectures will require bandwidths of 200GB/s to 1.0TB/s and will bring about the era of tera-scale computing. To meet these bandwidth demands, traditional electrical interconnect techniques requi...

Subthreshold VLSI circuits design received ample interest due to rapid growth of portable devices. The portable domain places in flexible limitation on the power dissipation. Though, device operating in subthreshold region shows huge potential towards satisfying the ultra low power requirement, it holds lots of difficult design issues. As integration density of interconnects increases at every ...

The importance of an interconnect pattern density model in ASIC design flow for a 90nm technology is presented. It is shown that performing the timing analysis at the worst-case corner model for interconnect variation, without the knowledge of interconnect pattern density, often results in overdesign. Our experiments on real ASIC products indicate that knowledge of interconnect pattern density ...

In order for the interconnect effects due to process-induced variations to be applied to the designs in 0.13μm and below, it is necessary to determine and characterize the realistic interconnect worstcase models with high accuracy and speed. This paper proposes new statisticallybased approaches to the characterization of realistic interconnect worstcase models which take into account process-in...