In this paper a novel algorithm for sound texture synthesis is presented. The goal of this algorithm is to produce new examples of a given sampled texture, the synthesized textures being of any desired duration. The algorithm is based on a montage approach to synthesis in that the synthesized texture is made up of pieces of the original sample concatenated together in a new sequence. This monta...

Image aesthetics assessment has been challenging due to its subjective nature. Inspired by the scientific advances in the human visual perception and neuroaesthetics, we design Brain-Inspired Deep Networks (BDN) for this task. BDN first learns attributes through the parallel supervised pathways, on a variety of selected feature dimensions. A high-level synthesis network is trained to associate ...

Conditional resource sharing has been identified as a possibility for optimizing high-level synthesis results. In this paper we propose a Hierarchical Conditional Dependency Graph representation that permits to treat conditional resource sharing in a generic fashion depending on the specific context, i.e. functional units, storage elements and interconnects. Resource usage conditions are repres...

For technologies with significant interconnection delays, optimal clock period selection before/during high-level synthesis is not practical. In our approach, we start with a synthesized RTL data path structure, perform place and route and back-annotate the interconnection delays. A set of potentially optimal clock periods are chosen by evaluating 'critical' paths to minimize the dead time asso...

A novel approach to high level synthesis of AsIcs based on a data driven execution model is presented. The synthesis procedure is directed at prodncing highly parallel Aslcs providing high throughput through pipelining. The major benefits of our approach are its potential for higher speed, ease of design, ease of verification and testing.

By considering test costs at behavioral level, test problems can be pointed out during the first phases of the design flow. Thus, in case either some testability problems are identified or the size (and hence the cost) of the test set results to be too high, the designer or the high level synthesis tool can modify the circuit to reduce such testability problems. The main problem is the correspo...

The document is organized as follows: chapter 2 describes the software installation process, chapter 3 shows the calling syntax of the SIF-to-CDFG format converter. Chapter 4 and 5 gives an overview on the handling of the graphical interfaces of the high-level transformation and high-level synthesis software tools. For theoretical background and realization details take a look at the research p...

This paper addresses the problem of development productivity on reconfigurable platforms. Due to the availability of generic low level tools and powerful logic synthesis tools, it becomes possible to define portable components that have both a high level behavior and attributes for physical synthesis. The behavior of a component can be fixed at compile time using concise specifications that wil...

The increasing demand for portable computing has elevated power consumption to be one of the most critical design parameters. A high-level synthesis system, HYPER-LP, is presented for minimizing power consumption in application specific datapath intensive CMOS circuits using a variety of architectural and computational transformations. The synthesis environment consists of high-level estimation...

This paper presents a method to carry out the register allocation phase of High Level Synthesis with testability considerations. Testability problems are identified and eliminated during this step turning testability/area tradeoff to account. It allows to decrease the cost related to the application of low-level DFT techniques.