This paper is produced and circulated privately and its inclusion in the conference does not constitute publication. Abstract The UK currently only has one new light rail (tram) scheme being implemented. By way of contrast, a number of high-quality bus systems have been developed; for example Cambridge and Luton Guided-busways, Thames Gateway Fastrack, Crawley Fastway and 'streetcar' bus operat...

While many current vehicle network systems for body bus applications use event triggered analysis processes, the deterministic point of view raises concerns about system timing due to message latency. This paper studies the latency performance characteristics of a typical body bus vehicle network using event triggered analysis over the CAN bus.

Inductive Cross-talk within IC Packaging is becoming a significant bottleneck in high speed inter chip communication. So the off-chip drivers typically source and sink 10 to 1000 drive internal loads. Thus simultaneously switching many off-chip drivers can cause large power (VDD) and ground current surges. These changes in current flow induce a voltage drop on the drivers’ local VDD rail and a ...

This paper presents a novel approach for fault type estimation in power systems. The Fault type estimation is the first step to estimate instantaneous voltage, voltage sag magnitude and duration in a three-phase system at fault duration. The approach is based on time-domain state estimation where redundant measurements are available. The current based model allows a linear mapping between the m...

TRIUMF’s Central Control System has a large investment in CAMAC. To protect this investment but allow the current trend of PCI-bus based computers to be supported, TRIUMF has configured a PCI to CAMAC system. In this setup, TRIUMF has connected PCI based computers into the CAMAC equipment of their Central Control System. DEC Alpha computers running OpenVMS have been interfaced via the PCI bus t...

Modern multi-processor system-on-chip (MPSoC) designs have high bandwidth constraints which must be satisfied by the underlying communication architecture. Traditional hierarchical shared bus communication architectures can only support limited bandwidths and are not scalable for very high performance designs. Bus matrix based communication architectures consist of several parallel busses which...

This paper examines the characteristics of intercity bus riders within Tennessee and proposes methods to identify service gaps and prioritize network expansion, particularly focusing on rural-urban connections. Data were collected through an on-board survey and compared with intercity auto trips. Compared to personal auto users, intercity bus riders are more likely to be of minority races, unem...

In a DC microgrid (DC-MG), the dc bus voltage is vulnerable to power fluctuation derived from the intermittent distributed energy or local loads variation. In this paper, a virtual inertia control strategy for DC-MG through bidirectional grid-connected converters (BGCs) analogized with virtual synchronous machine (VSM) is proposed to enhance the inertia of the DC-MG, and to restrain the dc bus ...