The paper proposed a new design for implementing semi-static flip-flop for low power and high performance applications. In this work, comparative analysis of six existing flip-flop designs along with the proposed design is made. The proposed design has better power, delay and PDP than the existing architectures. All simulations are performed on TSpice using BSIM models in 130 nm process node. T...

Flip (i) and flop (o) alternatively spliced variants of the four glutamate AMPA receptor subunits (GluR1-4) are differentially expressed in the CNS and can display distinct rates of desensitization that contribute to the heterogeneity of native AMPA receptor-dependent synaptic responses. In the present study, we initially compared the kinetics of desensitization in response to fast application ...

Transmembrane lipid translocation (flip-flop) processes are involved in a variety of properties and functions of cell membranes, such as membrane asymmetry and programmed cell death. Yet, flip-flops are one of the least understood dynamical processes in membranes. In this work, we elucidate the molecular mechanism of pore-mediated transmembrane lipid translocation (flip-flop) acquired from exte...

The four subunits of the AMPA-type glutamate receptor (GluR1-GluR4 or GluR-A-GluR-D) exist in two distinct forms, flip and flop, generated by alternative splicing of a 115 bp region. The GluR2 subunit plays a key role in determining the functional properties of the AMPA receptor channel. In this study, we examined the differences in kinetic properties between the flip and flop splice variants o...

This paper explores the energy-delay space of eight widely referred flip-flops in a 0.13μm CMOS technology. The main goal has been to find the smallest set of flip-flop topologies to be included in a “high performance” flip-flop cell library covering a wide range of power-performance targets. Based on our comparison results, transmission gate-based flipflops show the best power-performance trad...

OF THE THESIS Novel Flip-Flop Designs Tolerant to Soft-Errors and Crosstalk Effects by Aditya Jagirdar Thesis Director: Prof. Michael L. Bushnell The desire to make technology faster, smaller and more affordable compels us to shrink transistors further. As we realize designs with millions of transistors, most of the existing problems increase in severity and newer problems crop up. One major ne...

As the CMOS device becomes smaller, the process and aging variations become one of the major issues for circuit reliability and yield. Thus, a number of studies on the aging effects are currently underway. In this paper, we measure the setup/hold time and the variations considering aging effects such as a hot carrier injection (HCI) and negative bias temperature instability (NBTI) on flip-flop....

The paper introduces novel architectures for implementation of fully static master-slave flip-flops for low power, high performance, and high density. Based on the proposed structure, traditional C(2)MOS latch (tristate inverter/clocked inverter) based flip-flop is implemented with fewer transistors. The modified C(2)MOS based flip-flop designs mC(2)MOSff1 and mC(2)MOSff2 are realized using onl...

One of the effective ways to reduce power consumption is using clustered voltage scaling technique. The level converter flip-flop is needed to control static current when the block with Low Supply Voltage (VDDL) drives the block with High Supply Voltage (VDDH). One of the big challenges of design is that level converter flip-flop has low power and high speed. In this paper, pulse triggered leve...

In this paper, based on the coupled-mode and carrier rate equations, derivation of a dynamic model and numerically analysis of a MQW chirped DFB-SOA all-optical flip-flop is done precisely. We have analyzed the effects of strains of QW and MQW and cross phase modulation (XPM) on the dynamic response, and rise and fall times of the DFB-SOA all optical flip flop. We have shown that strained MQW a...