In this paper, an optical half adder is designed using photonic crystals. One of the features its small size. design structure, it has been tried to have a size, shorter delay and high contrast ratio so that can be used in integrated circuits. For sum carry outputs, obtained 15.4 dB 7.4 dB, respectively. addition, proposed structure size 70 µm2. The use simple point defects, caused maximum time...

we proposed a new adder design, called VariableLatency Adder (VL-adder). This technique allows the adder to work at a lower supply voltage than that required by a conventional adder, while maintaining the same throughput. The VL-adder design can be further modified to overcome the effects of Negative Bias Temperature Instability (NBTI) on circuit delay. By applying VL-adder concept to 64-bit ca...

In this paper, Carry Tree Adders are Proposed. Parallel prefix adders have the best performance in VLSI Design. Parallel prefix adders gives the best performance compared to the Ripple Carry Adder (RCA) and Carry Skip Adder (CSA). Here Delay measurements are done for Kogge-Stone Adder, Sparse Kogge-Stone Adder and Spanning Tree Adder. Speed of Kogge-Stone adder and Sparse Kogge-Stone adder have...

This paper proposes a full adder with minimum power consumption and lowloss with a central frequency of 1550nm using plasmonic Metal-Insulator-Metal (MIM)waveguide structure and rectangular cavity resonator. This full adder operates based onXOR and AND logic gates. In this full adder, the resonant wave composition of the firstand second modes has been used and we have ob...

In this paper, a novel design of an all-optical half-adder (HA) based on two two-ring resonators in two-dimensional square-lattice photonic crystal (PC) structure without nonlinear materials is proposed. The HA comprises AND and XOR gates where each gate composed cross-shaped waveguides 2D PC that are filled with silicon (Si) rods silica (SiO2). analyzed simulated using plane-wave expansion (PW...

A fast low-power 1-bit full adder circuit suitable for nano-scale CMOS implementation is presented. Out of the three modules in a common full-adder circuit, we have replaced one with a new design, and optimized another one, all with the goal to reduce the static power consumption. The design has been simulated and evaluated using the 65 nm PTM models.

Nonvolatile Logic-in-Memory Computing In article number 2200089, Chunxiang Zhu and co-workers propose demonstrate an electrochemical metallization memristor based on a solution-processed Pt/CuI/Cu structure. Owing to the efficient drift paths provided by Cu vacancies for cations in CuI, very small operating voltages are realized, contributing ultralow power consumption. Using CuI arrays, set of...

The proposed multiplexer-based novel 1-bit full adder cell is schematized by using DSCH2 and its layout is generated by using microwind VLSI CAD tool. The adder cell layout interconnect analysis is performed by using BSIM4 layout analyzer. The adder circuit is compared with other six existing adder circuits for parametric analysis. The proposed adder cell gives better performance than the other...

Abstract In this paper, a design and optimization of 4-bit absolute value detector is realized by using the CMOS technique, transmission gates, traditional comparator, which can compare two positive input values all expressed in binary form. To optimize overall performance detector, paper chooses to minimize number transistors simplifies circuit through logical analysis. As for calculating dela...