A compact 10 kW RF power amplifier at 352 MHz was developed at FREIA for the European Spallation Source, ESS. The specifications of ESS for the conception of amplifiers are related to its pulsed operation: 3.5 ms pulse length and a duty cycle of 5%. The realized amplifier is composed of eight kilowatt level modules, combined using a planar Gysel 8-way combiner. The combiner has a low insertion ...

This work describes the design of a double-precision radix-8 divider. Low-power techniques are applied in the design of the unit, and energy-delay tradeoffs considered. The energy dissipation in the divider can be reduced by up to 70% with respect to a standard implementation not optimized for energy, without penalizing the latency. The radix-8 divider is compared with one obtained by overlappi...

The implementation of a programmable high speed divider for a CMOS Frequency Synthesizer, using 0.35 μm CMOS technology, is described. The Frequency Synthesizer is part of a RF transceiver to work in the 2.4 GHz ISM (Industrial, Scientific and Medicine) band. The programmable divider employs: a divide-by-32/33 dual-modulus prescaler composed by a divide-by-4/5 synchronous counter, using the Ext...

A broad-band power divider is presented in CMOS technology. The devices are realized by postprocessing chips that are fabricated in a standard 1.2m CMOS process. Developed postprocessing includes wire bonding for ground equalization, deposition of a stress-compensation layer, and selective etching of the silicon substrate. By employing coupled coplanar transmission lines, the area of dividers i...

In this paper, the closed-form design method of an Nway dual-band Wilkinson hybrid power divider is proposed. This symmetric structure including N groups of two sections of transmission lines and two isolated resistors is described which can split a signal into N equiphase equiamplitude parts at two arbitrary frequencies (dual-band) simultaneously, where N can be odd or even. Based on the rigor...

In this paper, a low-power single-phase clock multiband flexible divider for Bluetooth, Zig-bee, and IEEE 802.15.4 and 802.11 a/b/g WLAN frequency synthesizers is proposed based on pulse-swallow topology and is implemented using a 0.18-m CMOS technology. The multiband divider consists of a proposed wideband multi-modulus 32/33/47/48 pre-scalar and an improved bit-cell for swallow (S) counter an...

This paper presents the size miniaturized and harmonic suppressed lossless 1:4 T-junction unequal power divider using an open complementary split ring resonator (OCSRR). By embedding the OCSRR structure in the microstrip transmission line, slow wave effect is introduced and thereby size reduction is achieved. The dimensions of OCSRR are optimized to reduce the length of high impedance and low i...

In this paper, Frequency divider by 2 circuit using D-flip-flop is done, based upon this a4/5 prescaler, 16/17 prescaler,32/33 prescalerareverified. Along with it the design of wide band multimodulus 320/321prescaler.CMOS single phase clock pre-scalar,wideband single phase clock 2/3 pre-scaler are also designed. A dynamic logic multiband flexible integer-N divider is designed which uses the wid...

A frequency divider based on injection-locked tunable ring oscillator is designed on 0.13-μm standard CMOS. The proposed design can achieve divide-by-4 in the frequency range of 58.75-66.3 GHz. The divider dissipates 49.5 to 54.5 mW power from a 1.5-V voltage supply. Key-Words: High-speed frequency dividers, Injection-locked tunable ring oscillator, Division range