We report the realization of electrical coupling between neurons and depletion type floating gate (FG) p-channel MOS transistors. The devices were realized in a shortened 0.5 microm CMOS technology. Increased boron implant dose was used to form the depletion type devices. Post-CMOS processing steps were added to expose the devices sensing area. The neurons are coupled to the polycrystalline sil...

This paper proposes a novel scheme of a gray scale fingerprint image for a high-accuracy capacitive sensor chip. The conventional grayscale image scheme uses a digital-to-analog converter (DAC) of a large-scale layout or charge-pump circuit with high power consumption and complexity by a global clock signal. A modified capacitive detection circuit for the charge sharing scheme is proposed, whic...

We present non-faradaic electrochemical recordings of exocytosis from populations of mast and chromaffin cells using chemoreceptive neuron MOS (CνMOS) transistors. In comparison to previous cell-FET-biosensors, the CνMOS features control (CG), sensing (SG) and floating gates (FG), allows the quiescent point to be independently controlled, is CMOS compatible and physically isolates the transisto...

The electrical characteristics of germanium p-metal– oxide–semiconductor (p-MOS) capacitor and p-MOS field-effect transistor (FET) with a stack gate dielectric of HfO2/TaOxNy are investigated. Experimental results show that MOS devices exhibit much lower gate leakage current than MOS devices with only HfO2 as gate dielectric, good interface properties, good transistor characteristics, and about...

A low voltage high performance design of operational transconductance amplifier is proposed in this paper. The architecture based on bulk driven quasi-floating gate metal oxide semiconductor field effect transistor (MOSFET) which supports operation and improves the gain amplifier. Besides to tail current source requirement (OTA) removed by using flipped follower structure at input pair along wi...

The MOS switch with bootstrapped technique is widely used in low-voltage switched-capacitor circuit. The switched-capacitor circuit with the bootstrapped technique could be a dangerous design approach in the nano-scale CMOS process due to the gate-oxide transient overstress. The impact of gate-oxide transient overstress on MOS switch in switchedcapacitor circuit is investigated in this work wit...

The floating-gate transistor can be used to design analog circuits, such as current mirrors [1], current scaler[2] and current multiplier [3, 4] and divider [4]. The multiple input floating-gate transistor can be used to design ultra lowvoltage “pseudo differential” pairs [1], hence ULV rail-to-rail amplifiers and analog multipliers are feasible using the floating-gate technique. In this paper ...

Gate dielectric leakage current becomes a serious concern as sub-20Å gate oxide prevails in advanced CMOS processes. Oxide this thin can conduct significant leakage current by various direct-tunneling mechanisms and degrade circuit performance. While the gate leakage current of MOS capacitors has been much studied, little has been reported on compact MOSFET modeling with gate leakage. In this w...

DEDICATION To my parents and my brother ACKNOWLEDGEMENTS I wish to gratefully acknowledge my advisor, Dr. Paul Hasler, for helping me during my stay at Gatech, providing an opportunity, guiding my research and reviewing this thesis. I also want to thank Dr. and Dr. Mark Smith for all the discussions we had and for reviewing this thesis. Many thanks also to the committee for the fruitful reviews...

The purpose of this paper is to illustrate a physicallybased model allowing the statistical simulations of oxide leakage currents in MOS transistors and Floating Gate memories. This model computes the leakage current through defects randomly generated in the oxide, in case accounting for the formation of percolation paths. Furthermore, a calculation procedure has been developed to calculate the...