One of the effective ways to reduce power consumption is using clustered voltage scaling technique. The level converter flip-flop is needed to control static current when the block with Low Supply Voltage (VDDL) drives the block with High Supply Voltage (VDDH). One of the big challenges of design is that level converter flip-flop has low power and high speed. In this paper, pulse triggered leve...

In this paper, based on the coupled-mode and carrier rate equations, derivation of a dynamic model and numerically analysis of a MQW chirped DFB-SOA all-optical flip-flop is done precisely. We have analyzed the effects of strains of QW and MQW and cross phase modulation (XPM) on the dynamic response, and rise and fall times of the DFB-SOA all optical flip flop. We have shown that strained MQW a...

Low scaling technology makes a significant reduction in dimension and supply voltage, and lead to new challenges about power consumption such as increasing nodes sensitivity over radiation-induced soft errors in VLSI circuits. In this area, different design methods have been proposed to low power flip-flops and various research studies have been done to reach a suitable hardened flip-flops. In ...

Cholesterol (CHOL) molecules play a key role in modulating the rigidity of cell membranes and controlling intracellular transport and signal transduction. Using an all-atom molecular dynamics approach, we study the process of CHOL interleaflet transport (flip-flop) in a dipalmitoylphosphatidycholine (DPPC)-CHOL bilayer over a time period of 15 μs. We investigate the effect of the flip-flop proc...

In this paper a novel low power double edge pulse triggered flip flop (FF) design is present. First, the pulse generation control logic by using the NAND function and is removed from the critical path to facilitate a faster discharge operation. A simple two transistor NAND gate design is used to reduce the circuit complexity. Second, a double edge conditional discharging flip flop is used to re...

This paper presents low power clock gating adiabatic D flip-flop using single phase sinusoidal power clock scheme. We propose the clock gated single phase Quasi-Static Energy Recovery Logic (QSERL) D flip-flop at 90nm CMOS technology. In the previously proposed QSERL logic, two phase sinusoidal power clocks were used that increased the hardware complexity and clocking issues. In this paper, sin...

This paper proposes a new double-edge-triggered implicitly level-converting flip-flop, suitable for a low-power and low-voltage design. The design employs a sense amplifier architecture to reduce the delay and power consumption. Experimentally, when implemented with a 130-nm, single-Vt and 0.84 V VDD process, it achieves 64% power-delay product (PDP) improvement, and moreover, 78% PDP improveme...

flip-flop circuit technique has been designed. CMOS new flip-flop circuit with CMOS domino logic which, All the flip-flops were designed using UMC 180. Recognize standard circuit symbols for D Type flip-flops. though can be largely prevented by using the Edge Triggered D Type flipflop illustrated in Fig 5.3.3. locked loop, using 32 nm CMOS technology. Here we design D flipflop for Phase locked ...

The pertinent choice of flip-flop topologies is an essential importance in the design of VLSI integrated circuits for high speed and high performance MODFET circuits. Understanding the suitability of flipflops and selecting the best topology for a given application is an important issue to fulfill the need of the design to satisfy low power and high performance circuit. This paper enumerates hi...