This paper proposes a Flash Analog to Digital Convsrter design based on the use of a Quantized Differential Comparator. The formulation explores the use of a systematically incorporated input offset voltage in a differential amplifier for quantizing the reference voltages necessary for Flash ADC architectures, thus eliminating the need for a passive resistor array for the purpose. This work is ...

The CMOS Monolithic Active Pixel Sensor (MAPS) for the International Linear Collider (ILC) vertex detector (VXD) expresses stringent requirements on their analog readout electronics, specifically on the analog-to-digital converter (ADC). This paper concerns designing and optimizing a new architecture of a low power, high speed, and small-area 4-bit column-parallel ADC Flash. Later in this study...

This paper describes a flash ADC using interpolation (IP) and cyclic background self-calibrating techniques. The proposed IP technique that is cascade of capacitor IP and gate IP with dynamic double-tail latched comparator reduces non-linearity, power consumption, and occupied area. The cyclic background self-calibrating technique periodically suppresses offset mismatch voltages caused by stati...

The real world signals are all analog in nature. So in order to convert the analog signals to digital efficiently an “Analog to digital converter” is required. In the digital domain, low power and low voltage requirements are becoming more important issues as the channel length of MOSFET shrinks below 0.25 sub-micron values. These trends present new challenges in ADC circuit design. In this pap...

The concept of time-domain reference-ladder for the implementation of fully-digital flash-ADCs is proposed in this work. The complete reference ladder is implemented using only digital circuits. Based on this concept, a flash ADC is proposed and implemented in this work using digital circuits, one comparator and a customized sample-and-ramp circuit. An unconventional time-to-digital conversion ...

This work describes a reconfigurable 10MS/s to 100MS/s, 0.5V to 1.2V, 0.98mm, 10b low-power 0.13um CMOS two-step pipeline ADC. The SHA employs gate-bootstrapped sampling switches and a two-stage amplifier based on a low-threshold NMOS differential input stage to obtain 10b accuracy even at a 0.5V supply. A signal-isolated all directionally symmetric layout reduces the MDAC capacitor mismatch wh...

Real-time on-chip measurement of bit error rate (BER) for high-speed analog-to-digital converters (ADCs) does not only require expensive multi-port high-speed data acquisition equipment but also enormous post-processing. This paper proposes a low-cost built-in-self-test (BIST) circuit for high-speed ADC BER test. Conventionally, the calculation of BER requires a high-speed adder. The presented ...

In this paper, a 6-bit 1 Gs/sec flash analog-to-digital converter (ADC) for low voltage and high speed system-on-chip (SoC) applications is presented. Simulated with the 45nm Predictive Technology Model, the results demonstrate INL < 0.5LSB, DNL < 0.8LSB and a signal to noise and distortion ratio of 31.9dB. The Threshold Inverter Quantization (TIQ) technique is used with WPMOS/WNMOS < 1 for man...

Over the past few years Ultra Wide Band (UWB) technology has taken the realms of communications circuit design to new levels. This paper demonstrates the design and simulation of a very high speed Flash Analog to Digital Converter (ADC) for UWB applications. The ADC was implemented in 90 nanometre (nm) CMOS design process. The converter works at an optimal sampling rate of 4.1 Gig-Samples per s...