Addition, as one of the fundamental math operations, is applied widely in Very-large-scale integration systems and digital signal processing, such that computational speed a system depends mainly on its adders. There are various types adders based different methods. A novel adder proposed which performs addition path with fewer number levels, and, hence, higher lower power consumption. The goal...

This paper proposes a full adder with minimum power consumption and lowloss with a central frequency of 1550nm using plasmonic Metal-Insulator-Metal (MIM)waveguide structure and rectangular cavity resonator. This full adder operates based onXOR and AND logic gates. In this full adder, the resonant wave composition of the firstand second modes has been used and we have ob...

Quantum-dot cellular automata (QCA) are a promising nanotechnology to implement digital circuits at the nanoscale. Devices based on QCA have the advantages of faster speed, lower power consumption, and greatly reduced sizes. In this paper, we are presented the circuits, which generate random numbers in QCA.  Random numbers have many uses in science, art, statistics, cryptography, gaming, gambli...

This article presents the design of a new asynchronous early output full adder which when cascaded leads to a relative-timed ripple carry adder (RCA). The relative-timed RCA requires imposing a very small relative-timing assumption to overcome the problem of gate orphans associated with internal carry propagation. The relative-timing assumption is however independent of the RCA size. The primar...

The proposed multiplexer-based novel 1-bit full adder cell is schematized by using DSCH2 and its layout is generated by using microwind VLSI CAD tool. The adder cell layout interconnect analysis is performed by using BSIM4 layout analyzer. The adder circuit is compared with other six existing adder circuits for parametric analysis. The proposed adder cell gives better performance than the other...

This paper presents a fast Motion Estimation algorithm concept with reduction in execution time, which provides low power consumption in the design of hardware architecture. A new VLSI architecture for Integer Motion Estimation based on the Full search algorithm is proposed.This architecture uses Sum Of Absolute Difference (SAD) operation,the commonly used metric to determine the best match of ...

Decimal hardware arithmetic units have recently regained popularity, as there is now a high demand for high performance decimal arithmetic. We propose a novel method for carry-free addition of decimal numbers, where each equally weighted decimal digit pair of the two operands is partitioned into two weighted bit-sets. The arithmetic values of these bit-sets are evaluated, in parallel, for fast ...