Abstract This article reports on the charge transport characteristics across potential barrier generated by a local dual‐gate modulation at surface of p‐doped graphene via contact fluorocarbon (CF) thin film. Owing to simple physical contact, strong electron affinity fluorine atoms in CF stably increases hole density graphene, which leads massive p‐doping effect graphene. Then, height can be an...

The influence of the nature of interface between organic semiconductor and gate dielectric on bias stress electrical stability of n-type C60-based organic field effect transistors (OFETs) was studied. The bias stress induced threshold voltage (Vth) shift was found to depend critically on the OFET device structure: the direction of V(th) shift in top-gate OFETs was opposite to that in bottom-gat...

The equations for the transfer characteristics and sub-threshold swing of dual-gate a-IGZO TFTs, when the top and bottom gate electrodes are connected (synchronized), are developed based on device physics. From these equations, it is found that synchronized DG aIGZO TFTs can be considered as conventional TFTs with modified gate capacitance and threshold voltage. The device parameters of coplana...

We propose a method for dual supply voltage digital design to reduce energy consumption without violating the given performance requirement. Although the basic idea of placing low voltage gates on non-critical paths is well known, a new two-step procedures does it so more efficiently. First, given a circuit and its nominal single supply voltage, we find a suitable value for a lower second suppl...

Poly-SiGe is investigated as the gate material for CMOS transistors with ultra-thin Hf02 gate dielectric. Compared with polySi, poly-SiGe reduces the gate depletion effect, and also results in thinner EOT of the gate dielectric after 1000°C annealing, with low gate leakage maintained. The Si interface quality is also better than that achieved with surface nitridation, which has been used to red...

Dual-metal gate CMOS devices with rapid-thermal chemicalvapor deposited (RTCVD) Si3N4 gate dielectric were fabricated using a self-aligned process. The gate electrodes are Ti and MO for the Nand PMOSFET respectively. Carrier mobilities are comparable to that predicted by the universal mobility model for Si02. C-V characteristics show good agreement with a simulation that takes quantum-mechanica...

The gate-oxide (aka gate tunneling or gate) leakage due to quantum-mechanical direct tunneling of carriers across the gate dielectric of a device is a major source power dissipation for sub-65nm CMOS circuits. In this paper a high-level (aka architecture) synthesis algorithm is presented that simultaneously schedules operations and binds to modules for gate leakage optimization. The algorithm u...