High-performance PMOSFETs with sub-50–nm gate-length are reported. A self-aligned double-gate MOSFET structure (FinFET) is used to suppress the short-channel effects. This vertical double-gate SOI MOSFET features: 1) a transistor channel which is formed on the vertical surfaces of an ultrathin Si fin and controlled by gate electrodes formed on both sides of the fin; 2) two gates which are self-...

Considerable challenges are encountered when bulk CMOS devices are scaled into the sub-100 nm regime for higher integrated circuit (IC) density and performance. Due to their excellent scalability and better immunity to short channel effects, double-gate (DG) MOSFETs are being easily assessed for CMOS applications beyond the 70 nm of the SIA roadmap. For channel lengths below 100 nm, DG MOSFETs ...

Self-aligned four-terminal (4T) planar metal double-gate (DG) polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) were fabricated on a glass substrate at a low temperature (LT), which is below 550◦C, to realize high performance and low power dissipation system-onglass (SoG). The top gate (TG) and bottom gate (BG) were formed from tungsten (W); the BG was embedded in the glass substra...

A phenomenological model, accounting for interface states at metal-semiconductor contacts, is proposed to explain particular gate-bias-dependent kinking in I-V characteristics sometimes observed MoS 2 FETs. The effect studied double-gate FETs by varying top-gate voltage (V xmlns:xlink="http://ww...

In this paper, the subthreshold swing was observed when stacked high-k gate oxide used for a junctionless double (JLDG) MOSFET. For purpose, model presented using series-type potential derived from Poisson equation. The results of in paper were good agreement with two-dimensional numerical values and those other papers. Using model, variation channel length, silicon thickness, dielectric consta...

Silicon-based CMOS technology can be scaled well into the nanometer regime. High-performance, planar, ultrathin-body devices fabricated on silicon-on-insulator substrates have been demonstrated down to 15-nm gate lengths. We have also introduced the FinFET, a double-gate device structure that is relatively simple to fabricate and can be scaled to gate lengths below 10 nm. In this paper, some of...

In this paper circuit design of reconfigurable dynamic logic based on double gate CNTFETs focusing on number of states of back gate voltages has been newly described. 16 function 9-10T DRDLC for two Boolean inputs with two states (+V, -V) of back gate voltages has been newly proposed. Using this 9-10T DRDLC the conventional 7T DRDLC with three states (+V, 0, -V) of back bate voltages is success...

In this paper, we propose a novel design analysis for a Junctionless Double Gate Vertical MOSFET (JLVMOS) with metal gate electrode and HfO2, for which the simulations have been performed using TCAD (ATLAS), The simulated results exhibits significant improvements in comparison to conventional JLVMOS device with a polysilicon gate electrode and ITRS values for different node technology . In plac...

This paper is investigated the low frequency noise behavior in subthreshold regime of gate-all-around silicon nanowire field effect transistors. Downscaling of multi gate structure beyond 50 nm gate length describes the quantum confinement related model. A drain current model has been described for output characteristics of silicon nanowire FET that is incorporated with velocity saturation effe...