Arithmetic Transform (AT) has been known under various names, including Inverse Integer Reed-Muller (IRM) transform. We outline the developments that place AT in the center of very practical arithmetic circuit applications, and explain the conditions for making the AT practical. We show that AT allows the only known scheme of treating all the approximation and imprecision sources of arithmetic ...

The paper presents a new approach to functional, bit-level verification of arithmetic circuits. The circuit is modeled as a network of adders and basic Boolean gates, and the computation performed by the circuit is viewed as a flow of binary data through such a network. The verification problem is cast as a Network Flow problem and solved using symbolic term rewriting and simple algebraic techn...

Nowadays reversible circuit designing is the emerging area of research. This design strategy aims towards the formation of digital circuits with ideally zero power dissipation. In this paper we have proposed a new reversible logic module to design a 4-bit binary 2‟s complement circuit. This complement circuit using reversible logic can be used to design other low loss Arithmetic circuit. Propos...

Agrawal and Vinay [AV08] have recently shown that an exponential lower bound for depth four homogeneous circuits with bottom layer of × gates having sublinear fanin translates to an exponential lower bound for a general arithmetic circuit computing the permanent. Motivated by this, we examine the complexity of computing the permanent and determinant via homogeneous depth four circuits with boun...

Recent advances of superconducting single-flux-quantum (SFQ) circuit technology make it attractive to investigate computing systems using SFQ circuits, where arithmetic circuits play important roles. In order to develop excellent SFQ arithmetic circuits, we have to design or select their underlying algorithms, called hardware algorithms, from different point of view than CMOS circuits, because ...

Agrawal and Vinay [AV08] showed how any polynomial size arithmetic circuit can be thought of as a depth four arithmetic circuit of subexponential size. The resulting circuit size in this simulation was more carefully analyzed by Korian [Koi12] and subsequently by Tavenas [Tav15]. We provide a simple proof of this chain of results. We then abstract the main ingredient to apply it to formulas and...

Sequential test generation becomes very time consuming when the circuit-under-test has many hard-to-test faults. This happens in cyclic sequential circuit. Design-for-testability method is applied on such circuit in order to speed up test generation time. However, this introduces huge area overhead. Alternatively, functional test generation is used to generate test sequences. In this option, st...

This paper presents a novel number system based on signed continuous valued digits. Arithmetic operations in this number system are performed using simple analog circuitry, in contrast to the conventional implementation of arithmetic units by Boolean or multiple-valued logic circuits. Unlike the limited precision offered by classical analog arithmetic circuits, the ensemble of continuous valued...