An 8-bit programmable square finder cum frequency divider architecture is presented. This special architecture includes a high speed parallel counter, clock trigger circuit, eight bit multiplier logic, sequence termination logic and sequence restarter logic. The entire architecture is divided into two parts: The frequency divider section and the square finder section. The frequency divider circ...

The Karlsruhe Tritium Neutrino Experiment (KATRIN) aims to determine the absolute mass of the electron antineutrino from a precise measurement of the tritium β-spectrum near its endpoint at 18.6 keV with a sensitivity of 0.2 eV/c. KATRIN uses an electrostatic retardation spectrometer of MAC-E filter type for which it is crucial to monitor high voltages of up to 35 kV with a precision and long-t...

The purpose of my project is to design & simulate the frequency divider using ADS software. My project is totally emphasized on the IEEE 802.11 a standard. The IEEE 802.11a describes the WLAN standard. The basis of the project is the SCL (Source Coupled Logic). This thesis organization provides an overview of the evolution of digitally programmable FREQUENCY DIVIDER using CMOS technology.

|A voltage controlled di erential injection locked frequency divider (VCDILFD) with a large locking range is designed in a 0:24 m CMOS technology. A 29% locking range is achieved by an optimal inductor design and also by employing high Q accumulation mode MOS varactors to change the free{running oscillation frequency of the divider. The measurement results show frequency division at 5GHz with m...

This paper presents implementation of a high speed, low noise and low power frequency divider based on current mode logic and cascade connection of divide-by-2/3 cells for high division range. The proposed divider is optimized for high frequency and low power operation. Integration of the proposed divider in a frequency synthesizer is an attractive option for the ultra-low power carrier signal ...

A compact fully integrated wideband six-port device composed of a suspended stripline Wilkinson power divider and three bias stripline of 3-dB quadrature directional couplers is presented. In order to integrate a six-port circuit, a multilayer circuit structure has been adopted by the via hole interconnection at the output port of the divider. The 3-dB quadrature directional coupler is composed...

A broad-band power divider is presented in CMOS technology. The devices are realized by postprocessing chips that are fabricated in a standard 1.2m CMOS process. Developed postprocessing includes wire bonding for ground equalization, deposition of a stress-compensation layer, and selective etching of the silicon substrate. By employing coupled coplanar transmission lines, the area of dividers i...

A dual-modulus (divide-by-16/17) prescaler has been designed using a 0.35μm CMOS technology. It consists of a divide-by-4/5 synchronous divider and a divideby-4 asynchronous divider, all implemented with MOS current mode logic. The operating frequency range is simulated to be from 0.8 to 3.1 GHz including all parasitics. The prescaler including the output buffers driving external 50Ω load draws...

Absbacl-An automatic Inductive Voltage Divider ( I M ) characterization method that can measure linearity by comparing WD’s with differeut structures is suggested. Structural models are employed to decompose an error vector into components that represent each divider. Initial tests at 400 Hz show that it is possible to assign independent errors due to the binary and decade structures with a 27 ...