Timing Speculation (TS) is a widely known method for realizing better-than-worstcase systems. Aggressive clocking, realizable by TS, enable systems to operate beyond specified safe frequency limits to effectively exploit the data dependent circuit delay. However, the range of aggressive clocking for performance enhancement under TS is restricted by short paths. In this paper, we show that incre...

This study introduces a reversible optical fulladder. Also optical NOT and NOR gates are implemented through Electro-Absorption-Modulator / Photo Detector (EAM/PD) pairs, were utilized for fulfilling reversible R gate. Then, reversible fulladder was designed based on the proposed reversible optical R gate. The operation of the suggested fulladder was simulated using Optispice and it was fou...

In this work two way partitioning of a circuit represented as a graph, is made using simulated annealing procedure and delay between the partitions is minimized. The various parameters used in the annealing process like initial temperature, cooling rate, and the threshold, given as a number of calculations , are changed and its influence on the delay between the partitions is discussed. Procedu...

It is well known that single-rail, bundled-delay circuits provide good area eficiency but it can be dificult to match them with appropriate delay models. Conversely delay insensitive circuits such as those employing dualrail codes are larger but it is easier to ensure timing correctness. In terms of speed, bundled-delay circuits need conservative timing but dual-rail circuits can require an app...

We present a simple electronic circuit that produces negative delays. When a pulse is sent to the circuit as input, the output is a pulse with a similar wave form that is shifted forward in time. The advance time or negative delay can be increased to the order of seconds so that we can observe the advance with the naked eye by observing two light emitting diodes that are connected to the input ...

This paper presents a new model for the statistical analysis of the impact of Random Telegraph Noise (RTN) on circuit delay. This RTN-aware delay model have been developed using Pseudo RTN based on a Markov process with RTN statistical property. We have also measured RTNinduced delay fluctuation using a circuit matrix array fabricated in a 65nm process. Measured results include frequency fluctu...

The speed of digital circuit is one of the most restricting factors in the deep sub-micron and multigigahertz integrated circuits design. It is directly dependent on the circuit delay. Scaling down the technologies and increasing the operational frequency make the delay problems more important. This paper studies the delay in digital circuits, starting from the design process, scaling down the ...

   This paper presents a novel design of quaternary logic gates using graphene nanoribbon field effect transistors (GNRFETs). GNRFETs are the alternative devices for digital circuit design due to their superior carrier-transport properties and potential for large-scale processing. In addition, Multiple-valued logic (MVL) is a promising alternative to the conventional binary logic design. Sa...