Shrinking transistor is undeniably important especially to reduce fabrication cost and to increase power efficiency of electronic devices. However, as fabrication technology progresses into deep submicron process, analog circuit design complexity grows significantly together with the increase in design time due to complex behaviour of short-channel Metal-Oxide-Semiconductor (MOS) transistor. Cu...

We have quantitatively described the transconductance improvement that can be obtained in deep submicron strained-Si on SixGe1 x MOSFET’s with respect to conventional Si ones due to velocity overshoot effects. We have done so making use of a Monte Carlo simulator and a recently developed transconductance analytical model.

Layout Optimization in Ultra Deep Submicron VLSI Design. (May 2006) Di Wu, B.E., Beijing University of Posts and Telecommunications; M.S., East Carolina University Co–Chairs of Advisory Committee: Dr. Rabi N. Mahapatra Dr. Jiang Hu As fabrication technology keeps advancing, many deep submicron (DSM) effects have become increasingly evident and can no longer be ignored in Very Large Scale Integr...

| Inverse modeling is a promising approach to know device structures made in experiments. We show our inverse modeling approach and its e ciency by demonstrating accurate extraction of deep submicron MOSFET structures. We also show that our approach can predict device performance to optimize its structure for required speci cation.

This paper investigates dipolar ordering phenomena in chains of deep-submicron size, strongly coupled nanomagnets by Magnetic Force Microscopy. We will examine effects influencing the length o f antiferromagnetic ordering in these chains. Experimental observations will be compared to single-domain simulations and we will discuss methods to achieve the possible longest-range ordering. Keywords-n...

As MOSFET devices are aggressively scaled into the deep submicron regime quantum mechanical effects become increasingly important. We compare the recently proposed effective potential formalism with the density gradient approach for first order quantum simulations of sub 0.1μm MOSFETs within a modified drift diffusion framework.

We developed and characterized Monolithic pixel detectors in deep-submicron Fully Depleted (FD) Silicon On Insulator (SOI) technology. This paper presents the first studies of total dose effects from ionizing radiation performed on single transistor test structures. This work shows how the substrate bias condition during irradiation heavily affects the resulting radiation damage.

Deep submicron technology introduces strong linkages between process, design, and reliability. Papers in this session talk about the effect of process defects on chip reliability estimation, measurement of circuit delay variations due to process variability, and future trends in power supply distribution as a result of interconnect scaling.