This paper presents a simulator of a multithread processor, which is developed, with a minimum architectural impact, on a conventional RISC platform. The multithread processor supports a mixture of controland data-flow model of execution with hardware primitives for scheduling and synchronization. The simulator permits, by changing the processor parameters such as the cache size, the number of ...

This paper reviews and extends an analytical model for the behavior of dataflow graphs with data-dependent control flow. The number of tokens produced or consumed by each actor is given as a symbolic function of the Booleans in the system. Long-term averages can be analyzed to determine consistency of token flow rates. Short-term behavior can be analyzed to construct an annotated schedule, or a...

Dynamically reconfigurable computing systems (DRCS) provides an intermediate tradeoff between flexibility and performance of computing systems design. Unfortunately, designing DRCS has a highly complex and formidable task. The lack of tools and design flows discourage designers from adopting the reconfigurable computing technology. A UML-based design flow for DRCS is proposed in this article. T...

At the class testing level, state-based testing and data flow testing techniques have been employed. However, while the former only involves the variables that have an effect on the behaviour of the object under test, it is possible for errors to occur in variables, which do not define an object’s state. Data flow testing has been applied to generate test cases for testing classes using data fl...