Full Adder is one of the critical parts of logical and arithmetic units. So, presenting a low power full adder cell reduces the power consumption of the entire circuit. Also, using Nano-scale transistors, because of their unique characteristics will save energy consumption and decrease the chip area. In this paper we presented a low power full adder cell by using carbon nanotube field effect tr...

In this paper, we propose and evaluate a novel design of a lightly doped drain and source carbon nanotube field effect transistor (LDDS-CNTFET) with a negative differential resistance (NDR) characteristic, called negative differential resistance LDDS-CNTFET (NDR-LDDS-CNTFET). The device was simulated by using a non equilibrium Green’s function method. To achieve this phenomenon, we have created...

In this paper, we propose and evaluate a novel design of a lightly doped drain and source carbon nanotube field effect transistor (LDDS-CNTFET) with a negative differential resistance (NDR) characteristic, called negative differential resistance LDDS-CNTFET (NDR-LDDS-CNTFET). The device was simulated by using a non equilibrium Green’s function method. To achieve this phenomenon, we have created...

Nanoscale carbon-nanotube field-effect transistors (CNTFETs) have been a focus of recent studies in next-generation semiconductor architecture. However, in numerous CNTFETs that have been proposed, process variations, as well as measurement fluctuations, have occurred regularly, hampering the development of these devices for practical applications. Moreover, it is difficult to control the condu...

The aim of this paper is to design Carbon Nanotube Field Effect Transistor-based (CNTFET-based) combinational circuits with improved Power Delay Product (PDP). Ternary logic circuits have attracted substantial interest due to their capability of increasing information content per unit area. As a result, the geometry-dependent threshold voltage of CNTFETs is effectively used to design a ternary ...

The shrinkage in size of VLSI chips as well as improved energy efficiency is the need of the modern digital era. Using ternary logic instead of conventional binary logic helps to reduce circuit complexity and hence reduces chip area. Carbon nanotubes FET (CNTFET) are preferred over CMOS for logic design due to its high performance i.e. excellent transport property, low resistivity and higher cu...

This chapter describes a reconfigurable computing architecture based on clusters of regular matrices of fine-grain dynamically reconfigurable cells using double-gate carbon nanotube field effect transistors (DG-CNTFET), which exhibit ambivalence (p-type or n-type behaviour depending on the backgate voltage). Hierarchical function mapping methods suitable for the cluster of matrices structure ha...

A novel and robust scheme for radix-4 Booth scheme implemented in Carbon Nanotube Field-Effect Transistor (CNTFET) technology has been presented in this paper. The main advantage of the proposed scheme is its improved speed performance compared with previous designs. With the help of modifications applied to the encoder section using Pass Transistor Logic (PTL), the corresponding capacitances o...