In this paper we describe a hybrid element method which combines the boundary element method (BEM) and the finite element method (FEM) to calculate circuit models for layout dependent capacitances. The method can handle irregularities in the stratification of the layout of the integrated circuits (IC’s). We present a stand-alone extraction program which we developed for validation and testing p...

It is essential to accurately predict parasitics and the numerous high frequency effects while designing RF integrated circuits (RFICs). A traditional RFIC design flow involves schematic design and simulation, followed by layout, then by post-layout verification and extraction. However, this traditional flow usually leads to multiple iterations between schematic and layout designs and ends up w...

An increasingly urgent topic for the realization of densely packed (mixed signal) integrated circuits is prevention of cross-talk via the substrate. Due to decreasing distances between components and increasing operating frequencies, the coupling between components and/or circuit blocks becomes stronger and affects the circuit behaviour more and more. This paper proposes a Boundary Element Meth...

In our digital design laboratory we have replaced the traditional wired circuit modules by workstations equipped with an extension board containing a single FPGA. This hardware is supplemented with a set of software tools consisting of a compiler for the circuit specification language Lola, a graphical layout editor for design entry, and a checker to verify conformity of a layout with its speci...

The radiation response of a 0.25 μm silicon-on-sapphire CMOS technology is characterized at the transistor and circuit levels utilizing both standard and enclosed layout devices. The threshold-voltage shift is less than 170 mV and the leakage-current increase is less than 1 nA for individual standard-layout nMOSFET and pMOSFET devices at a total dose of 100 krad(SiO2). The increase in power sup...

This paper presents a new circuit design for digital pulse-width modulators (DPWM). In this paper, we improve the structure of hybrid DPWM by utilization of the separation of MSB/LSB group. In addition, a delay line element is shared by MSB/LSB group to reduce the power consumption. The new DPWM prototype circuit operates at 600 MHz clock frequency and has 1.1-mW power consumption. An experimen...

We address the problem of crosstalk computation and reduction using circuit and layout techniques in this paper. We provide easily computable expressions for crosstalk amplitude and pulse width in resistive, capacitively coupled lines. The expressions hold for nets with arbitrary number of pins and of arbitrary topology under any specified input excitation. Experimental results show that the av...

Crosstalk between printed circuit board (PCB) traces in switching power supplies may cause high electromagnetic interference emission. PCB layout plays an important part and a genetic algorithm (GA) is used to produce a layout with reduced crosstalk. A coupling index and a new way of representing a trace for the GA process is presented.

As the minimum feature size shrinks down far below sub-wavelength, Design for Manufacturability or layout regularity plays an important role for maintaining pattern fidelity in photolithography. However, it also incurs overheads in circuit performances due to parasitic capacitance. In this paper, we examine the effect of layout regularity on printability and circuit performance by lithography s...

Quantum circuit design flow consists of two main tasks: synthesis and physical design. In the current flows, two procedures are performed subsequently and without any information sharing between two processes that can limit the optimization of the quantum circuit metrics; synthesis converts the design description into a technology-dependent netlist and then, physical design takes the fixed netl...