RC4 Stream cipher is well known for its simplicity and ease to develop in software. But here, in the proposed design we have heighlighted the modified hardware implémentation of RC4. As RC4 is the most popular stream cipher. The proposed design performs reading and swapping simultaneously in one clock cycle. The proposed design also highlights the adder part which enhances the architecture spee...

Ripple-carry adder (RCA) is among the most common type of adder. However, it not preferred in many applications because its high latency. In this paper, two architectures high-speed parallel RCA (PRCA) along with fault detection and localization are proposed, reduced overhead as compared carry look-ahead (CLA). proposed approach, divided into blocks, where initial input for each block will be g...

This paper presents novel architectures for fast binary addition which can be implemented using multi-plexers only. Binary addition is carried out using a fast redundant-to-binary converter. It is shown that appropriate encoding of the redundant digits and re-casting the binary addition as a redundant-to-binary conversion reduces the latency of addition from Wt fa to Wt mux where t fa and t mux...

The demand of low power high speed circuits are in demand with the increasing universal growth in electronic system and the loss of information is not acceptable as with single loss of a bit information the energy loss is equal to kTlog2 joules/bit. Reversible logic can be of prominent interest to design low power arithmetic and data path units for digital signal processing applications, such a...

Extremely energy-efficient logic devices are required for future low-power high-performance computing systems. Superconductor electronic technology has a number of families. Among them is the adiabatic quantum-flux-parametron (AQFP) family, which adiabatically switches (QFP) circuit when it excited by an AC power-clock. When compared to state-of-the-art CMOS technology, AQFP circuits have advan...

The Residue Number System (RNS) is a non-weighted system that is very efficient in digital signal processing and communicational applications. The previous proposed methods for the residue to binary (R/B) conversions are based on the Chinese Reminder Theorem (CRT) or Mixed Radix Conversion (MRC). These theorems are difficult to implement. In this paper, we present a new highspeed ROM-less resid...

The growing design complexity has attracted the designs with Reconfigurable fabrics, where adaptable fabrics are utilized to solve the computational problems. Reconfigurable computing provides the flexibility in arriving at the problem specific architectures which helps in improving the performance due to custom approach. In this paper, a flexible reconfigurable architecture with different adde...

In this paper, we propose 128-bit Kogge-Stone, Ladner-Fischer, Spanning tree parallel prefix adders and compared with Ripple carry adder. In general N-bit adders like Ripple Carry Adders (slow adders compare to other adders), and Carry Look Ahead adders (area consuming adders) are used in earlier days. But now the most Industries are using parallel prefix adders because of their advantages comp...

This paper presents the design of high performance and ultralow power 8-bit carry-look-ahead adder circuits using two-phase modified dual-threshold voltage (dual-VT) domino logic method with the feed through logic concept. The proposed concepts are provides lower delay and dynamic power consumption; due to these two advantages it perform better in high fan-out and high switching frequencies. Th...

The consumption of power has become an important issue in modern VLSI design. Power consumption can be reduced by replacing some flip-flops with fewer multi-bit flip-flops. Multi-bit flip-flop is one of the methods for clock power consumption reduction. This project focuses on reduction of power using multi-bit flipflops by clock synchronization. Two single bit flip-flops are synchronized with ...