Although a relatively young conference, the International Conference on Computer Design (ICCD) has over the last five years filled an important niche in the computer industry. ICCD 86 is scheduled for October 6-9, 1986, at the Rye Town Hilton, Port Chester, New York. It is sponsored by the IEEE Circuits and Systems Society and the IEEE Computer Society in cooperation with the IEEE Electron Devi...

The simulated annealing (SA) algorithm [14] [5] has been applied to every di cult optimization problem in VLSI CAD. Existing SA implementations use monotone decreasing, or cooling, temperature schedules motivated by the algorithm's proof of optimality as well as by an analogy with statistical thermodynamics. This paper gives strong evidence that challenges the correctness of using such schedule...

The development of a high-level language compiler for a micro-programmable processing element (PE) in the MARS multicomputer is described. MARS, an MIMD message passing machine, was designed to speed up VLSI CAD and similar other non-numerical applications. The need for sup port of a high-level language at the PE level of a multicomputer is considered, and the choice of C as an appropriate prog...

Abstract This paper proposes a novel VLSI architecture for an FIR filter chip providing variable-length taps. To change the number of taps, we propose two special features called a data-reuse structure and a recurrent-coefficient scheme. These features consist of several MUXs and registers and reduce the number of gates over 20 % compared with existing chips using an address generation unit and...

We present an analytical method to perform the design of the I/O subsystem of an IC given its throughput requirements. Our method can be used to select the IC package, along with the bus size and speed so as to minimize I/O cost. We have validated our model by conducting simulations on three industry-standard packages while varying the bus width, slew rate, and signal-to-power/ground ratio. Our...

Methods based on AND/OR graph representations of Boolean relations provide a promising new way of approaching VLSI CAD design automation problems. AND/OR graphs can represent any Boolean network and they allow for systematic reasoning through the application of the technique of recursive learning. An approach to build and analyze AND/OR graphs that makes use of hashing techniques in a way simil...

by Eric W. Johnson With the development of improved fabrication processes, more responsibility is placed on circuit designers to develop circuits that are tolerant of fluctuations in the fabrication process. To achieve this higher reliability, designers must have access to actual data variations in the fabrication process. Historically, this process data has been collected from test measurement...

Despite advances in CAD tools, layout errors resulting in electrical shorts between complex nets continue to cause trouble in many VLSI design projects. Locating the geometrical features causing shorts is often the most vexing problem faced during the layout verification process. Although this problem is common and important, there seems to be no published literature dealing with short location...

Adequate information modeling in non-standard application areas (e.g. engineering applications such as CAD/CAM, VLSI design or knowledgebased applications) requires the abstraction concepts of classification, aggregation, generalization, and association. The Molecule-Atom Data model (MAD) designed for the effective support of such an information model is justified and described with its essenti...

Standard cell placement and routing is an important open problem in current CAD VLSI research. We present a novel approach to placement and routing in standard cell arrays inspired by geometric constraint usage in traditional CAD systems. Placement is performed by an algorithm that places the standard cells in a spiral topology around the center of the cell array driven by a DFS on the intercon...