In this paper, a new algorithm and a new BIST structure for efficiently testing dual port memories that is used widely as embedded memory, is proposed. The proposed test algorithm is able to detect the dual port memories faults and has shorter test time and the test patterns in comparison to existing test algorithms. In addition, the presented BIST has efficient structure that requires lesser h...

.......................................................................................................................................... ii Acknowledgments.......................................................................................................................... iv List of Tables ......................................................................................................

This paper presents aa new test resource partitioningg scheme that is aa hybridd approachh betweenn external testingg andd BIST. It reduces tester storage requirements anddtesterbandwidthhrequirementsbyordersof magnitude comparedd too conventional external testing, but requires muchh less areaa overheadd thann aa full BIST implementationn providingg the same fault coverage. The proposedd approa...

A new hybrid BIST scheme is proposed which is based on using an “incrementally guided LFSR.” It very efficiently combines external deterministic data from the tester with on-chip pseudo-random BIST. The hardware overhead is very small as a conventional STUMPS architecture [1] is used with only a small modification to the feedback of the LFSR which allows the tester to incrementally guide the LF...

BIST is a technique aimed to: Avoiding the usage of expensive ATE Increase the fault tolerance since it add more access to the internal points Allow the application of at-speed test and reduce the test time. It is mandatory to consider the BIST as a test solution when the design flow and the design area can afford it.

A software component must be tested every time it is reused, to guarantee the quality of both the component itself and the system in which it is to be integrated. To reduce testing costs, we propose a model to build highly testable components by embedding testing and monitoring mechanisms inside them. The approach is useful to component developers, who can use these built-in test capabilities i...

1.Problem of High-Speed Interface Macro Testing Because the function of the chip is guaranteed, the high-speed function test is important. Moreover, it is an important issue in LSI test how cheaply to do this test. The high-speed function test in an internal logical circuit can be tested by using BIST methodology and the output clock of PLL with a low-speed and low-cost ATE. However, the high-s...

In this paper a novel hierarchical DfT methodology is presented which is targeted to improve the delay fault testability for external testing and scanbased BIST. After the partitioning of the design into high frequency macros, the analysis for delay fault testability already starts in parallel with the implementation at the macro level. A specification is generated for each macro that defines t...

The main goal of this thesis was to develop an experimental environment for the test time minimization problem. It assumes Hybrid BIST architecture and targets System-on-Chip designs. The thesis is based on methodology developed during the work and demonstrates the feasibility of the proposed methodology together with experimental results. First two sections of this thesis explore the actuality...

We propose a procedure for designing an LFSRbased circuit for masking of unknown output values that appear in the output response of a circuit tested using LBIST. The procedure is based on reseeding of the LFSR to mask unknown output values while allowing fault effects to propagate. To determine the seeds, the output response of the circuit is partitioned into a minimal number of fragments, and...